Abstract: A system includes host interface circuitry to interact with a host system and that includes an address translation circuit, which includes request staging queues to buffer the address translation requests, each includes a virtual address and received from a host interface circuit. Pending response queues buffer respective address translation requests that are waiting for an address translation from the host system while maintaining an order as received within the request stage queues. Reordering buffers reorder address translations, which are to be supplied to the host interface circuits, according to the order maintained within the pending response queues, each address translation includes a physical address mapped to the virtual address of a corresponding address translation request. A cache stores multiple of the address translations, associated with the address translation requests, for future access by the host interface circuits.

Abstract: A system and method for detecting and correcting memory errors in CXL components is presented. The method includes receiving, into a decoder, a memory transfer block (MTB), wherein the MTB comprises data and parity information, wherein the MTB is arranged in a first dimension and a second dimension. An error checking and a correction function on the MTB is performed using a binary hamming code logic within the decoder in the first dimension. An error checking and a correction function on the MTB is performed using a non-binary hamming code logic within the decoder in the second dimension. Further, the binary hamming code logic and the non-binary hamming code logic perform the error checking on the MTB simultaneously.

Abstract: A system and method for detecting and correcting memory errors in CXL components is presented. The method includes receiving, into a decoder, a memory transfer block (MTB), wherein the MTB comprises data and parity information, wherein the MTB is arranged in a first dimension and a second dimension. An error checking and a correction function on the MTB is performed using a binary hamming code logic within the decoder in the first dimension. An error checking and a correction function on the MTB is performed using a non-binary hamming code logic within the decoder in the second dimension. Further, the binary hamming code logic and the non-binary hamming code logic perform the error checking on the MTB simultaneously.

Abstract: Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.

Abstract: A command processing method and a storage controller are provided. The command processing method includes performing a command merging process on commands sequentially received by a command queue. The command merging process includes an initialization step and multiple iterations. The initialization step includes transmitting the commands from the command queue to a continuity checking pool (CCP), transmitting an initial command of the commands from the CCP to a continuity list (CL) and setting a range of the CL. Each of the iterations includes transmitting the commands from the command queue to the CCP; determining whether the commands in the CCP and the range of the CL conform to a continuity condition; and when the commands in the CCP and the range conform to the continuity condition, appending the first command to the CL and resetting the range of the CL according to the first command.

Abstract: A data management method and a storage controller are provided. The method includes: receiving write sectors corresponding to a write command and transmitting the write sectors to a partial block buffer or a full block buffer; when the write sectors corresponding to a first block are transmitted to the partial block buffer, starting a timer corresponding to the first block; when the partial block buffer receives first write sectors corresponding to the first block and the first write sectors and the write sectors corresponding to the first block in the partial block buffer form a full first block, the first block is transmitted to the full block buffer before or when the timer is expired; and when the timer is expired and the full first block is not yet formed in the partial block buffer, performing a read-modify-write operation according to the write sectors corresponding to the first block.

Abstract: A data management method and a storage controller are provided. The method includes: receiving write sectors corresponding to a write command and transmitting the write sectors to a partial block buffer or a full block buffer; when the write sectors corresponding to a first block are transmitted to the partial block buffer, starting a timer corresponding to the first block; when the partial block buffer receives first write sectors corresponding to the first block and the first write sectors and the write sectors corresponding to the first block in the partial block buffer form a full first block, the first block is transmitted to the full block buffer before or when the timer is expired; and when the timer is expired and the full first block is not yet formed in the partial block buffer, performing a read-modify-write operation according to the write sectors corresponding to the first block.

Abstract: A command processing method and a storage controller are provided. The command processing method includes performing a command merging process on commands sequentially received by a command queue. The command merging process includes an initialization step and multiple iterations. The initialization step includes transmitting the commands from the command queue to a continuity checking pool (CCP), transmitting an initial command of the commands from the CCP to a continuity list (CL) and setting a range of the CL. Each of the iterations includes transmitting the commands from the command queue to the CCP; determining whether the commands in the CCP and the range of the CL conform to a continuity condition; and when the commands in the CCP and the range conform to the continuity condition, appending the first command to the CL and resetting the range of the CL according to the first command.

Abstract: A command processing method and a storage controller using the same are provided. The command processing method includes: receiving a plurality of I/O commands; categorizing the I/O commands into a plurality of groups according to a processor effort index of the I/O commands; selecting a first group from the groups, resetting a timer and obtaining an expiration time corresponding to the first group according to the I/O commands of the first group, and executing the I/O commands of the first group; and selecting a second group from the groups and resetting the timer when the expiration time of the first group expires, wherein when the processor effort index of the first group is less than a threshold, a clock frequency of the processor is lowered before the expiration time expires.

Abstract: A data transmission method is provided. The method includes receiving a transmission command from a host system, wherein the transmission command includes a starting logical block address, a number of logical blocks, a first physical region page pointer, and a second physical region page pointer, wherein the transmission command is configured to transmit target data between at least one target logical block of a rewritable non-volatile memory module and at least one target memory page of a host memory; buffering a plurality of entries of at least one physical region page pointer list corresponding to the transmission command if the second physical region page pointer is a first list starting address of a first physical region page pointer list corresponding to the transmission command; and transmitting corresponding data according to the buffered entries.

Abstract: A command processing method and a storage controller using the same are provided. The command processing method includes: receiving a plurality of I/O commands; categorizing the I/O commands into a plurality of groups according to a processor effort index of the I/O commands; selecting a first group from the groups, resetting a timer and obtaining an expiration time corresponding to the first group according to the I/O commands of the first group, and executing the I/O commands of the first group; and selecting a second group from the groups and resetting the timer when the expiration time of the first group expires, wherein when the processor effort index of the first group is less than a threshold, a clock frequency of the processor is lowered before the expiration time expires.

Abstract: A data transmission method, a memory storage device and a memory control circuit unit are provided. The method includes: obtaining a first command from a host system and counting a first time value; performing a first access operation corresponding to the first command on the rewritable non-volatile memory module; and generating a first completion message corresponding to completion of the first access operation and buffering the first completion message in a buffer area; and transmitting the first completion message buffered in the buffer area to the host system if the first time value meets a first waiting time value. Accordingly, a data access speed detected by the host system is stabilized.

Abstract: A data transmission method, a memory storage device and a memory control circuit unit are provided. The method includes: obtaining a first command from a host system and counting a first time value; performing a first access operation corresponding to the first command on the rewritable non-volatile memory module; and generating a first completion message corresponding to completion of the first access operation and buffering the first completion message in a buffer area; and transmitting the first completion message buffered in the buffer area to the host system if the first time value meets a first waiting time value. Accordingly, a data access speed detected by the host system is stabilized.

Abstract: A data transmission method is provided. The method includes receiving a transmission command from a host system, wherein the transmission command includes a starting logical block address, a number of logical blocks, a first physical region page pointer, and a second physical region page pointer, wherein the transmission command is configured to transmit target data between at least one target logical block of a rewritable non-volatile memory module and at least one target memory page of a host memory; buffering a plurality of entries of at least one physical region page pointer list corresponding to the transmission command if the second physical region page pointer is a first list starting address of a first physical region page pointer list corresponding to the transmission command; and transmitting corresponding data according to the buffered entries.

Abstract: A data reading method is provided. The method includes receiving a read command from a host system, wherein the read command includes a starting logical block address, a number of logical blocks, a first physical region page pointer, and a second physical region page pointer, and the read command is configured to read target data from at least one target logical block of a rewritable non-volatile memory module and write the read target data into at least one target memory page of a host memory; obtaining an address of each of the target memory pages respectively corresponding to the at least one target logical block according to the read command; and selecting a first target logical block from the at least one target logical block, and writing the read first target data into a first target memory page according to the obtained address of the first target memory page.