Patents by Inventor Di Tang

Di Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11289409
    Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: March 29, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 11276218
    Abstract: Embodiments of the present disclosure provide a method for skinning a character model, a device for skinning a character model, a computer readable medium, and an electronic device, and relate to the field of computer technology. The method comprises: obtaining a first character model and a corresponding skeleton structure; determining a vertex attribute of the first character model and a connecting relationship between the vertices; performing a nonlinear transformation process on the vertex attribute to obtain the first feature, and performing a graph convolution process on the connecting relationship and the first feature to obtain a second feature; determining a global feature and a local feature of the character model according to the second feature; and determining a target feature representing a binding relationship between the first character model and the skeleton hierarchy according to the global feature and the local feature.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 15, 2022
    Assignee: NETEASE (HANGZHOU) NETWORK CO., LTD.
    Inventors: Lijuan Liu, Di Tang, Yi Yuan, Changjie Fan
  • Publication number: 20200410733
    Abstract: Embodiments of the present disclosure provide a method for skinning a character model, a device for skinning a character model, a computer readable medium, and an electronic device, and relate to the field of computer technology. The method comprises: obtaining a first character model and a corresponding skeleton structure; determining a vertex attribute of the first character model and a connecting relationship between the vertices; performing a nonlinear transformation process on the vertex attribute to obtain the first feature, and performing a graph convolution process on the connecting relationship and the first feature to obtain a second feature; determining a global feature and a local feature of the character model according to the second feature; and determining a target feature representing a binding relationship between the first character model and the skeleton hierarchy according to the global feature and the local feature.
    Type: Application
    Filed: March 31, 2020
    Publication date: December 31, 2020
    Applicant: NETEASE (HANGZHOU) NETWORK CO.,LTD.
    Inventors: Lijuan LIU, Di TANG, Yi YUAN, Changjie FAN
  • Publication number: 20200144167
    Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 10566271
    Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 18, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Publication number: 20170232668
    Abstract: A 3D printing system comprises: a digital micro-mirror device (DMD) mobile device (1); a light source (3), fixed on said DMD mobile device (1) for emitting ultraviolet light, blue light or visible light; multiple DMDs (2) carried on the DMD mobile device (1) for receiving the ultraviolet light, blue light or visible light emitted by the light source (3) and generating 3D object section light; a lens (4) for receiving the 3D object section light reflected by the DMDs (2) and refracting and amplifying the 3D object section light; a material box (5) for containing and providing printing materials; a workbench (6), wherein the 3D object section light refracted by the lens irradiates the printing materials provided by the material box (5) to solidify the printing materials into a 3D object carried on the workbench (6); and a lifting device (7) for lifting the workbench (6).
    Type: Application
    Filed: May 26, 2014
    Publication date: August 17, 2017
    Inventors: Zhen Shen, Di TANG, Gang Xiong, Feiyue Wang
  • Publication number: 20170200671
    Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 13, 2017
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 9190296
    Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: November 17, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 9177837
    Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: November 3, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8975734
    Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8977871
    Abstract: A system comprises a plurality of processor cores. The processor cores may comprise one or more application processor (AP) cores and a boot strap processor (BSP) core. A basic input/output system (BIOS) comprises an I/O device module to call a stall function in response to an I/O operation, a power management module that couples to the I/O device and a timer module that couples to the power management module. The power management module is to adjust a timer period of the timer module based on a stall delay of the stall function. The power management module may hook the stall function and compare the stall delay with a predetermined threshold and set the timer period to the stall delay in response to determining that the stall delay is longer. The power management module may put the BSP in a sleep mode during the timer period to save power.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: March 10, 2015
    Assignee: Intel Corporation
    Inventors: Di Tang, Vincent Zimmer, James Edwards, Rahul Khanna, Yufu Li, Abdul Bailey
  • Publication number: 20140315351
    Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.
    Type: Application
    Filed: June 30, 2014
    Publication date: October 23, 2014
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8835225
    Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 16, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fu-Di Tang, Ching-Chiuan Wei, Yung-Chih Lin
  • Publication number: 20140206146
    Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Publication number: 20140162409
    Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 12, 2014
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Fu-Di Tang, Ching-Chiuan Wei, Yung-Chih Lin
  • Patent number: 8716861
    Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 6, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8624368
    Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: January 7, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fu-Di Tang, Ching-Chiuan Wei, Yung-Chih Lin
  • Patent number: 8607040
    Abstract: Methods and apparatuses for re-instantiating a firmware environment that includes one or more firmware functions available at pre-boot time when transitioning the computing device from a first, higher power consumption state to a second, lower power consumption state. The firmware environment determines whether a cryptographic signature on a firmware volume is verified; whether hardware resources of the computing device requested by a manifest of the firmware volume are available; and whether a firmware module of the firmware volume is compatible with installed firmware of the firmware environment. If so, the firmware environment reserves space in a memory to accommodate resources used by the firmware module, and executes the firmware module with the computing device in the second, lower power consumption state.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: December 10, 2013
    Assignee: Intel Corporation
    Inventors: Vincent J. Zimmer, Abdul M. Bailey, James W. Edwards, Rahul Khanna, Yu Fu Li, Di Tang
  • Publication number: 20130311665
    Abstract: A system, device, and method for facilitating wireless communications during a pre-boot phase of a computing device includes establishing a communications interface between a unified extensible firmware interface executed on the computing device and a wireless transceiver of the computing device during a pre-boot phase of the computing device. An OOB processor of the computing device processes data communications between the unified extensible firmware interface and the wireless communication circuit during the pre-boot phase by reformatting the data communications between wired and wireless communication standards.
    Type: Application
    Filed: February 25, 2013
    Publication date: November 21, 2013
    Inventors: Abdul M. Bailey, Di Tang, Rahul Khanna, Vincent J. Zimmer, Kevin Y. Li, James W. Edwards
  • Patent number: D935232
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 9, 2021
    Inventor: Di Tang