Abstract: A lighting device includes a base, a panel assembly, and a power supply assembly. The panel assembly is at least partially connected to the base and includes a luminous body. The power supply assembly is connected to the lighting device. The panel assembly includes a main panel and a plurality of auxiliary panels. The main panel is fixedly connected to the base, a first auxiliary panel among the plurality of auxiliary panels is rotatably connected to the main panel, and a second auxiliary panel among the plurality of auxiliary panels is rotatably connected to the first auxiliary panel.

Abstract: A lighting device includes a base, a panel assembly, and a power supply assembly. The panel assembly is at least partially connected to the base and includes a luminous body. The power supply assembly is connected to the lighting device. The panel assembly includes a main panel and a plurality of auxiliary panels. The main panel is fixedly connected to the base, a first auxiliary panel among the plurality of auxiliary panels is rotatably connected to the main panel, and a second auxiliary panel among the plurality of auxiliary panels is rotatably connected to the first auxiliary panel.

Abstract: A method of bonding first die(s) to a wafer and a die-stack structure includes: providing a first layer of first die(s), each of the first die(s) including a first metal layer; providing the wafer, which includes a second metal layer; bonding the first die(s) to the wafer; forming an insulating layer and a hole, the insulating layer covering the wafer around the first die(s) or filling gap(s) between the first die(s), the hole formed in the insulating layer around the first die(s); forming an interconnect structure in the hole, the first metal layer, the second metal layer and the interconnect structure are electrically connected, thus establishing electrical connection between the first die(s) and the wafer. In this method, it is unnecessary to form TSV within the first die(s), reducing difficulties in the design of internal wiring within the first die(s) and resulting in area savings of the first die(s).

Abstract: A method of manufacturing a semiconductor device includes: providing bonded first and second wafers; forming a patterned insulating layer on the second substrate, the patterned insulating layer having first holes and dummy holes both exposing the second substrate; forming a protective layer, which fills a partial depth of the dummy holes and covers side surfaces of the first holes; forming through-silicon vias (TSVs); and forming a second metal layer including an interconnect metal layer and a dummy metal layer, the interconnect metal layer filling the TSVs and electrically connected to the first metal layer, the dummy metal layer filling the dummy holes. The formation of the dummy metal layer is integrated in the TSV process and is therefore done without using any additional process or adding additional cost to enable uniform pattern density (e.g., metal density) across the surface of the second wafer and enhanced CMP uniformity.

Abstract: Disclosed in the present disclosure are a semiconductor device and manufacturing method thereof. The method comprises: bonding the front surface of a top wafer to the front surface of a first wafer, and enabling the front surface of the top wafer to face upwards and the front surface of the first wafer to face downwards; bonding the front surface of a second wafer to the back surface of the first wafer to form a bonding structure, and enabling the front surface of the second wafer to face downwards; flipping the bonding structure to enable the front surface of the first wafer and the front surface of the second wafer to face upwards, and forming a pad pin in a top chip substrate.

Abstract: A wafer structure, a method for manufacturing the wafer structure, and a chip structure are provided. In a case that two wafers are bonded together, an opening extending through a substrate of one of the wafers is formed at a back surface of the wafer, and a concave-convex structure is formed in the dielectric layer under the opening. At least one of concave portions of the concave-convex structure extends to expose the interconnection layer of the wafer structure. A pad is formed on the concave-convex structure by filling the concave-convex structure, and the pad has the same concave-convex arrangement as the concave-convex structure. In this way, the pad has a concave-convex surface, such that a contact surface area of the pad is effectively increased without increasing a floor space of the pad.

Abstract: A wafer structure, a method for manufacturing the wafer structure, and a chip structure are provided. In a case that two wafers are bonded together, an opening extending through a substrate of one of the wafers is formed at a back surface of the wafer, and a concave-convex structure is formed in the dielectric layer under the opening. At least one of concave portions of the concave-convex structure extends to expose the interconnection layer of the wafer structure. A pad is formed on the concave-convex structure by filling the concave-convex structure, and the pad has the same concave-convex arrangement as the concave-convex structure. In this way, the pad has a concave-convex surface, such that a contact surface area of the pad is effectively increased without increasing a floor space of the pad.