Abstract: A Content Addressable Memory (CAM) array includes a first and a second cell structure sharing a cell boundary. The first cell structure includes a first storage circuit and a first comparator circuit, the first comparator circuit includes a first transistor having a gate, a drain, and a source. The second cell structure includes a second storage circuit and a second comparator circuit, the second comparator circuit includes a second transistor having a gate, a drain, and a source. The CAM array further includes a first shared source contact landing on the source of the first transistor and the source of the second transistor. The first shared source contact connects the source of the first transistor to the source of the second transistor. And the first shared source contact extends across the shared cell boundary from the first cell structure to the second cell structure.

Abstract: A device includes a first transistor including a first drain/source terminal and a second transistor including a first gate terminal. A first conductive path is electrically connected between the first drain/source terminal and the first gate terminal. The first conductive path includes a first conductive via electrically connected between the first drain/source terminal and a first track of a first conductive layer, and a second conductive via electrically connected between the first track of the first conductive layer and a first track of a second conductive layer.