Abstract: For printed circuit board (“PCB”) design, methods, systems, and apparatuses are disclosed. One apparatus includes a component ID module that identifies a PCB component to be placed on a current board design; a search module that displays one or more instances of previous board designs containing the identified PCB component, wherein displaying the one or more instances of previous board designs containing the identified PCB component comprises displaying a region surrounding the identified PCB component; and an import module that imports a selected portion of a board design into the current board design from a selected one of the instances of previous board designs containing the identified PCB component.

Abstract: A child component ID module identifies child components connected to a parent component in response to selection of the parent component for placement on a PCB. The child components identified from component connections of a logic design. A child placement module places the child components around the parent component after placement of the parent component, where each child component is placed in compliance with constraints of the child components. A constraint highlight module identifies, on a PCB layout, an allowable area for component placement and prohibited areas for non-placement after selection of the component. The component is a parent component or a child component identified from component connections of a logic design of an electronic circuit design. The apparatus includes a constraint de-highlight module that removes identification on the PCB layout of the allowable area and the one or more prohibited areas in response to placement of the component.

Abstract: A controlled-impedance printed circuit board (PCB) design program allows interactive movement of features from one of the vertically-stacked layers of the design to another layer in a graphical interface. The movement either moves a region of a layer of the PCB design, or moves an entire layer in a layer-swapping operation. The program computes modified widths of circuit traces of the first layer of the controlled-impedance printed circuit board design according to an impedance control value of the controlled-impedance printed circuit board design and according to a new position of the circuit traces caused by a movement of the features of the first layer to the second layer. The program also checks for violation of reference plane requirements for critical signals and warns the designer if such a violation is present.

Abstract: For printed circuit board (“PCB”) design, methods, systems, and apparatuses are disclosed. One apparatus includes a component ID module that identifies a PCB component to be placed on a current board design; a search module that displays one or more instances of previous board designs containing the identified PCB component, wherein displaying the one or more instances of previous board designs containing the identified PCB component comprises displaying a region surrounding the identified PCB component; and an import module that imports a selected portion of a board design into the current board design from a selected one of the instances of previous board designs containing the identified PCB component.

Abstract: Identifying and resolving issues with placement of plated through vias in voltage divider regions of a printed circuit board (“PCB”) layout. Search parameters indicate an area of the PCB layout to be analyzed, and vias meeting the search parameters are evaluated for placement issues. Upon detecting a placement issue for a via, a solution is determined that addresses and resolves the placement issue of the via. The resolution in an embodiment includes modifying an adjacent power shape, modifying a region between shapes, and/or modifying via placement to minimize risks that include potential shorting, partially-connected vias, and/or poor plated barrel adhesion.

Abstract: A printed circuit board (PCB) stack having a plurality of layers is received. A conformal coating layer is applied to one or more external layers of the plurality of layers. A conductive ink is applied to one or more portions of the protective conformal coating layer to form one or more conductive features on the protective conformal coating layer.

Abstract: A controlled-impedance printed circuit board (PCB) design program allows interactive movement of features from one of the vertically-stacked layers of the design to another layer in a graphical interface. The movement either moves a region of a layer of the PCB design, or moves an entire layer in a layer-swapping operation. The program computes modified widths of circuit traces of the first layer of the controlled-impedance printed circuit board design according to an impedance control value of the controlled-impedance printed circuit board design and according to a new position of the circuit traces caused by a movement of the features of the first layer to the second layer. The program also checks for violation of reference plane requirements for critical signals and warns the designer if such a violation is present.

Abstract: A child component ID module identifies child components connected to a parent component in response to selection of the parent component for placement on a PCB. The child components identified from component connections of a logic design. A child placement module places the child components around the parent component after placement of the parent component, where each child component is placed in compliance with constraints of the child components. A constraint highlight module identifies, on a PCB layout, an allowable area for component placement and prohibited areas for non-placement after selection of the component. The component is a parent component or a child component identified from component connections of a logic design of an electronic circuit design. The apparatus includes a constraint de-highlight module that removes identification on the PCB layout of the allowable area and the one or more prohibited areas in response to placement of the component.

Abstract: The present disclosure provides a method, computer program product, and system of document implementation tool for pcb refinement. In some embodiments, the system includes a current data object with at least a PCB design, a PCB data store, a feature identifier configured to identify one or more features in at least the current PCB design, a comparison engine, configured to compare features in the current PCB design and known features in the PCB data store, a classification engine configured to classify one or more discrepancies between the current PCB design and the PCB data store based on a size of each of the one or more discrepancies, a determination engine configured to determine changes needed to resolve the one or more discrepancies, and a reporting engine configured to report the one or more discrepancies to a user.

Abstract: Identifying and resolving issues with placement of plated through vias in voltage divider regions of a printed circuit board (“PCB”) layout. Search parameters indicate an area of the PCB layout to be analyzed, and vias meeting the search parameters are evaluated for placement issues. Upon detecting a placement issue for a via, a solution is determined that addresses and resolves the placement issue of the via. The resolution in an embodiment includes modifying an adjacent power shape, modifying a region between shapes, and/or modifying via placement to minimize risks that include potential shorting, partially-connected vias, and/or poor plated barrel adhesion.

Abstract: The present disclosure provides a method, computer program product, and system of document implementation tool for pcb refinement. In some embodiments, the system includes a current data object with at least a current PCB design, a printed circuit board (PCB) data store, where the plurality of data objects has known features, a feature identifier configured to identify one or more features in at least the current PCB design, a comparison engine, configured to compare features in the current PCB design and known features in the PCB data store that have been linked to one or more manufacturing defects, a classification engine configured to classify one or more feature between the current PCB design and the PCB data store, a determination engine configured to determine one or more changes in the current PCB design likely to decrease an occurrence of a manufacturing defect.

Abstract: The present disclosure provides a method, computer program product, and system of document implementation tool for pcb refinement. In some embodiments, the system includes a current data object with at least a PCB design, a PCB data store, a feature identifier configured to identify one or more features in at least the current PCB design, a comparison engine, configured to compare features in the current PCB design and known features in the PCB data store, a classification engine configured to classify one or more discrepancies between the current PCB design and the PCB data store based on a size of each of the one or more discrepancies, a determination engine configured to determine changes needed to resolve the one or more discrepancies, and a reporting engine configured to report the one or more discrepancies to a user.

Abstract: The present disclosure provides a method, computer program product, and system of document implementation tool for pcb refinement. In some embodiments, the system includes a current data object with at least a current PCB design, a printed circuit board (PCB) data store, where the plurality of data objects has known features, a feature identifier configured to identify one or more features in at least the current PCB design, a comparison engine, configured to compare features in the current PCB design and known features in the PCB data store that have been linked to one or more manufacturing defects, a classification engine configured to classify one or more feature between the current PCB design and the PCB data store, a determination engine configured to determine one or more changes in the current PCB design likely to decrease an occurrence of a manufacturing defect.

Abstract: Via array placement on a printed circuit board (PCB) outline including receiving, by a PCB design module, via array data from a user; generating, by the PCB design module, a via array based on the via array data from the user, including placing the via array on the PCB outline, wherein the via array comprises a grid of vias; detecting, by the PCB design module, that a first PCB element has been placed on top of a first portion of the via array on the PCB outline; removing, by the PCB design module, the first portion of the via array under the first PCB element, wherein a second portion of the via array remains on the PCB outline after removing the first portion of the via array; and generating, by the PCB design module, a PCB design document using the PCB outline and the second portion of the via array.

Abstract: Dynamic electronic printed circuit board (PCB) design is provided. A test net on a PCB is dynamically created utilizing a first rule defining a net parameter and a second rule defining a padstack geometric parameter. A first evaluation of one or more nets having a first padstack is performed against the first rule. A second evaluation of both the first padstack and a reference padstack determined to be adjacently positioned to the first padstack is performed against the second rule. Based on the evaluations, a potential test net having a potential test padstack is dynamically selected from the evaluated nets. The selected potential test net is dynamically transformed into the test net. The dynamic transformation includes modifying the potential test padstack and/or the reference padstack utilizing the second rule. The dynamic creation of the test net improves the efficiency of electronic PCB design by mitigating time and footprint consumption.

Abstract: An approach is provided in which an information handling system creates a printed circuit board (PCB) layout based upon a set of packaged components. The information handling system modifies the PCB layout based upon an adjustment of the set of packaged components and generates board design data based on the modified PCB layout. In turn, the information handling system simulates the PCB layout using the board design data.

Abstract: Dynamic electronic printed circuit board (PCB) design is provided. A voltage split having a first geometric shape in a first layer of the PCB is identified. Based on the voltage split, a boundary having a second geometric shape is created in an adjacently positioned layer of the PCB with respect to the first layer. A net having at least two pins is dynamically routed in the PCB. An intersection of the net with the first boundary is identified and dynamically resolved.

Abstract: Via array placement on a printed circuit board (PCB) outline including receiving, by a PCB design module, via array data from a user; generating, by the PCB design module, a via array based on the via array data from the user, including placing the via array on the PCB outline, wherein the via array comprises a grid of vias; detecting, by the PCB design module, that a first PCB element has been placed on top of a first portion of the via array on the PCB outline; removing, by the PCB design module, the first portion of the via array under the first PCB element, wherein a second portion of the via array remains on the PCB outline after removing the first portion of the via array; and generating, by the PCB design module, a PCB design document using the PCB outline and the second portion of the via array.

Abstract: Dynamic electronic printed circuit board (PCB) design is provided. A test net on a PCB is dynamically created utilizing a first rule defining a net parameter and a second rule defining a padstack geometric parameter. A first evaluation of one or more nets having a first padstack is performed against the first rule. A second evaluation of both the first padstack and a reference padstack determined to be adjacently positioned to the first padstack is performed against the second rule. Based on the evaluations, a potential test net having a potential test padstack is dynamically selected from the evaluated nets. The selected potential test net is dynamically transformed into the test net. The dynamic transformation includes modifying the potential test padstack and/or the reference padstack utilizing the second rule. The dynamic creation of the test net improves the efficiency of electronic PCB design by mitigating time and footprint consumption.

Abstract: An approach is provided in which an information handling system creates a printed circuit board (PCB) layout based upon a set of packaged components. The information handling system modifies the PCB layout based upon an adjustment of the set of packaged components and generates board design data based on the modified PCB layout. In turn, the information handling system simulates the PCB layout using the board design data.