Abstract: A parallel input/output combined encoding and syndrome generating system encodes two information symbols per clock cycle, and thereafter, produces two redundancy symbols per clock cycle. For an n-symbol code word with 2k information symbols cn−1, to cn−2k, the symbols cn−1, cn−3, cn−5 . . . are supplied, in turn, to a first input line while the symbols cn−2, cn−4, cn−6, . . . are supplied, in turn, to a second input line. In a first clock cycle, the symbol cn−1 is combined with the contents of the R registers, where R is the number of redundancy symbols, and the contents are multiplied by the respective roots of the generator polynomial. The products then are combined with the paired symbol cn−2 and the resulting sums are multiplied also by the roots of the generator polynomial. These products are then summed in a chain of R adders and the respective registers are appropriately updated with the results of the encoding of the two symbols.

Abstract: A method and system for verifying the integrity of data written to a mass memory medium. A local memory is directed by local memory control logic to store a data block that is received from a host microprocessor and that is to be written to the mass memory medium. The data block comprises a sequence of data symbols. An ECC encoder encodes the stored data block with error correction data. The error correction data comprises a sequence of error correction symbols that are appended to the data symbols. The data and error correction symbols are stored in the mass memory and immediately retrieved. An ECC decoder receives the retrieved data and error correction symbols from the mass memory and the data and error correction symbols of the encoded data block from the encoder. In response, the decoder generates an error status signal when more than a predetermined threshold number of the retrieved data and error correction symbols are improperly stored in the mass memory.