Patents by Inventor Diana Llera-Hurlburt

Diana Llera-Hurlburt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Edge seal for a semiconductor device
    Patent number: 7163883
    Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: January 16, 2007
    Assignee: International Business Machines Corporation
    Inventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
  • Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor
    Patent number: 7098676
    Abstract: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: August 29, 2006
    Assignee: International Business Machines Corporation
    Inventors: William F. Landers, Thomas M. Shaw, Diana Llera-Hurlburt, Scott W. Crowder, Vincent J. McGahay, Sandra G. Malhotra, Charles R. Davis, Ronald D. Goldblatt, Brett H. Engel
  • Multi-functional structure for enhanced chip manufacturibility & reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor
    Publication number: 20040129938
    Abstract: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.
    Type: Application
    Filed: January 8, 2003
    Publication date: July 8, 2004
    Applicant: International Business Machines Corporation
    Inventors: William F. Landers, Thomas M. Shaw, Diana Llera-Hurlburt, Scott W. Crowder, Vincent J. McGahay, Sandra G. Malhotra, Charles R. Davis, Ronald D. Goldblatt, Brett H. Engel
  • Method of making an edge seal for a semiconductor device
    Patent number: 6734090
    Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: May 11, 2004
    Assignee: International Business Machines Corporation
    Inventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
  • Edge seal for a semiconductor device
    Publication number: 20040087078
    Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 6, 2004
    Inventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
  • Edge seal for a semiconductor device
    Publication number: 20030157794
    Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.
    Type: Application
    Filed: February 20, 2002
    Publication date: August 21, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel