Patents by Inventor Diane Garza Flemming

Diane Garza Flemming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8745622
    Abstract: Standalone software performance optimizer systems for hybrid systems include a hybrid system having a plurality of processors, memory operably connected to the processors, an operating system including a dispatcher loaded into the memory, a multithreaded application read into the memory, and a static performance analysis program loaded into the memory; wherein the static performance analysis program instructs at least one processor to perform static performance analysis on each of the threads, the static performance analysis program instructs at least one processor to assign each thread to a CPU class based on the static performance analysis, and the static performance analysis program instructs at least one processor to store each thread's CPU class.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Greg R. Mewhinney, Diane Garza Flemming, David B. Whitworth, William A. Maron, Mysore Sathyanarayana Srinivas
  • Patent number: 8566539
    Abstract: A method, system, and computer usable program product for managing thermal condition of a memory are provided in the illustrative embodiments. A condition that a threshold value of a thermal condition of the memory has been exceeded or is likely to be exceeded is identified. A portion of a first workload is identified as being a cause of exceeding the threshold. A second portion of a second workload is identified, the second portion not causing the threshold to be exceeded when executed. A set of operations corresponding to the first portion is interleaved with a second set of operations corresponding to the second portion. The interleaved first and second portions of the first and second workloads are executed, causing the thermal condition of the memory to remain below the threshold. The second portion may use a second memory, a second area of the memory, or a combination thereof when executing.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Diane Garza Flemming, Ghadir Robert Gholami, Octavian Florin Herescu, William A Maron, Mysore Sathyanarayana Srinivas
  • Patent number: 8453122
    Abstract: A symmetric multi-processor SMP system includes an SMP processor and operating system OS software that performs automatic SMP lock tracing analysis on an executing application program. System administrators, users or other entities initiate an automatic SMP lock tracing analysis. A particular thread of the executing application program requests and obtains a lock for a memory address pointer. A subsequent thread requests the same memory address pointer lock prior to the particular thread release of that lock. The subsequent thread begins to spin waiting for the release of that address pointer lock. When the subsequent thread reaches a predetermined maximum amount of wait time, MAXSPIN, a lock testing tool in the kernel of the OS detects the MAXSPIN condition. The OS performs a test to determine if the subsequent thread and address pointer lock meet the list of criteria set during initiation of the automatic lock trace method.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Diane Garza Flemming, Eric Philip Fried, Greg R. Mewhinney, David Blair Whitworth
  • Patent number: 8438338
    Abstract: An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.
    Type: Grant
    Filed: August 15, 2010
    Date of Patent: May 7, 2013
    Assignee: International Business Machines Corporation
    Inventors: Diane Garza Flemming, William A. Maron, Ram Raghavan, Mysore Sathyanarayana Srinivas, Basu Vaidyanathan
  • Patent number: 8417889
    Abstract: An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Diane Garza Flemming, William A. Maron, Ram Raghavan, Mysore Sathyanarayana Srinivas, Basu Vaidyanathan
  • Patent number: 8412907
    Abstract: A method of allocating resources in a data processing system is disclosed. The method includes an application designing a page reallocation scheme and sending said page reallocation scheme from said application to a kernel service that is responsible for allocation of storage locations.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: April 2, 2013
    Assignee: Google Inc.
    Inventors: Andrew Dunshea, Diane Garza Flemming
  • Patent number: 8407499
    Abstract: Handling requests for power reduction by first enabling a request for an amount of power change, e.g. reduction by any partition. In response to the request for power reduction, an equal proportion of the whole amount of power reduction is distributed between each of a set of cores providing the entitlements to the partitions, and the entitlement of the requesting partition is reduced by an amount corresponding to the whole amount of the power change.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K Anand, Diane Garza Flemming, William A Maron, Mysore Srinivas
  • Patent number: 8392659
    Abstract: A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Diane Garza Flemming, William A. Maron, Mysore Sathyanarayana Srinivas
  • Patent number: 8145870
    Abstract: The present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, a kernel service creates a storage map, and sending said storage map to an application. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating a cache map. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating an indication of one or more storage locations that have been allocated to store information for the application. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating the storage map in response to receiving a request for the storage map from the application.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: March 27, 2012
    Assignee: International Business Machines Corporation
    Inventors: Andrew Dunshea, Diane Garza Flemming
  • Publication number: 20120042131
    Abstract: An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.
    Type: Application
    Filed: August 15, 2010
    Publication date: February 16, 2012
    Applicant: International Business Machines Corporation
    Inventors: Diane Garza Flemming, William A. Maron, Ram Raghavan, Mysore Sathyanarayana Srinivas, Basu Vaidyanathan
  • Publication number: 20110258468
    Abstract: Handling requests for power reduction by first enabling a request for an amount of power change, e.g. reduction by any partition. In response to the request for power reduction, an equal proportion of the whole amount of power reduction is distributed between each of a set of cores providing the entitlements to the partitions, and the entitlement of the requesting partition is reduced by an amount corresponding to the whole amount of the power change.
    Type: Application
    Filed: April 20, 2010
    Publication date: October 20, 2011
    Applicant: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, William A. Maron, Mysore Srinivas, Diane Garza Flemming
  • Patent number: 8024738
    Abstract: A system for managing processor cycles. A set of uncapped partitions are identified that are ready-to-run in response to unused processor cycles being present in a dispatch window. A number of candidate partitions are identified from the identified set of uncapped partitions based on a history of usage where each identified partition used at least 100 percent of its entitlement in a predefined number of previous dispatch windows. Then, a partition is selected from the number of candidate partitions based on a lottery process of the candidate partitions.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Diane Garza Flemming, Octavian Florin Herescu
  • Patent number: 7962677
    Abstract: A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: William A. Maron, Diane Garza Flemming, Ghadir Robert Gholami, Mysore Sathyanarayana Srinivas, Octavian Florin Herescu
  • Publication number: 20110107031
    Abstract: A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores.
    Type: Application
    Filed: November 5, 2009
    Publication date: May 5, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vaijayanthimala K. Anand, Diane Garza Flemming, William A. Maron, Mysore Sathyanarayana Srinivas
  • Publication number: 20110022803
    Abstract: An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 27, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diane Garza Flemming, William A. Maron, Ram Raghavan, Mysore Sathyanarayana Srinivas, Basu Vaidyanathan
  • Patent number: 7721047
    Abstract: In view of the foregoing, the shortcomings of the prior art cache optimization techniques, the present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, an application requests a kernel cache map from a kernel service and the application receives the kernel. The application designs an optimum cache footprint for a data set from said application. The objects, advantages and features of the present invention will become apparent from the following detailed description. In one embodiment of the present invention, the application transmits a memory reallocation order to a memory manager. In one embodiment of the present invention, the step of the application transmitting a memory reallocation order to the memory manager further comprises the application transmitting a memory reallocation order containing the optimum cache footprint to the memory manager.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: May 18, 2010
    Assignee: International Business Machines Corporation
    Inventors: Andrew Dunshea, Diane Garza Flemming
  • Patent number: 7711905
    Abstract: A system for managing data in a plurality of storage locations. In response to a least recently used algorithm wanting to move data from a cache to a storage location, an aging table is searched for an associated entry for the data. In response to finding the associated entry for the data in the aging table, an indicator is enabled on the data. In response to determining that the indicator is enabled on the data, the data is kept in the cache despite the least recently used algorithm wanting to move the data to the storage location.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: Diane Garza Flemming, Octavian Florin Herescu, William A. Maron, Mysore Sathyanarayana Srinivas
  • Patent number: 7698529
    Abstract: A method is provided for a data processing system configured to include multiple logical partitions, wherein resources of the system are selectively allocated among respective partitions. In the method, an entity such as a Partition Load Manager or a separate background process is used to manage resources based on locality levels. The method includes the step of evaluating the allocation of resources to each of the partitions at a particular time, in order to select a partition having at least one resource considered to be of low desirability due to its level of locality with respect to the selected partition. The method further comprises identifying each of the other partitions that has a resource matching the resource of low desirability, and determining the overall benefit to the system that would result from trading the resource of low desirability for the matching resource of each of the identified partitions.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jos Manuel Accapadi, Andrew Dunshea, Diane Garza Flemming, Catherine Moriarty Nunez
  • Publication number: 20100017551
    Abstract: A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 21, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William A. Maron, Diane Garza Flemming, Ghadir Robert Gholami, Mysore Sathyanarayana Srinivas, Octavian Florin Herescu
  • Publication number: 20090138911
    Abstract: A method, medium and implementing processing system, are provided in which premium programming content is included in a standard program broadcasting system. The added content is stored at a user site for subsequent viewing at the user's convenience. The receipt and storing of the premium programming is accomplished without interfering with the receipt of standard broadcast signals. The premium programming, in one example, is transmitted and incrementally received and stored on a user's system even while standard programming is received and viewed by the user. When all of the broadcast increments of a premium program have been received and the premium program has been stored in the user's system, a signal is provided to the user to indicate the availability of the premium program for selective viewing by the user.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 28, 2009
    Inventors: Diane Garza Flemming, Ghadir Robert Gholami, Octavian Florin Herescu, William A. Maron, Mysore Sathyanarayana Srinivas