Patents by Inventor Diane M. Christie

Diane M. Christie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5358826
    Abstract: A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.
    Type: Grant
    Filed: May 8, 1992
    Date of Patent: October 25, 1994
    Assignee: Cray Research, Inc.
    Inventors: Richard R. Steitz, Diane M. Christie, Eugene F. Neumann, Melvin C. August, Stephen Nelson
  • Patent number: 5182420
    Abstract: A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.
    Type: Grant
    Filed: April 9, 1990
    Date of Patent: January 26, 1993
    Assignee: Cray Research, Inc.
    Inventors: Richard R. Steitz, Diane M. Christie, Eugene F. Neumann, Melvin C. August, Stephen Nelson
  • Patent number: 5127570
    Abstract: A flexible automated bonding apparatus electrically interconnects integrated circuit carriers, printed circuit boards, and other devices. A metallized interconnect pattern is deposited on the surface of the substrate. The metallized interconnects in the pattern span apertures created in the substrate using an excimer laser. Thus, the metallized interconnects can be electrically bonded through the apertures to elements lying underneath the substrate.
    Type: Grant
    Filed: June 28, 1990
    Date of Patent: July 7, 1992
    Assignee: Cray Research, Inc.
    Inventors: Richard R. Steitz, Melvin C. August, Diane M. Christie, Deanna M. Dowdle, Dean B. Dudley, Stephen E. Nelson, Eugene F. Neumann, Paul E. Schroeder
  • Patent number: H1153
    Abstract: A hermetically sealed carrier for integrated circuits has an IC placed on a carrier substrate, and an electrical lead apparatus, comprised of a highly heat resistant substrate with a metallized interconnect pattern deposited thereon, connected to the IC and brought out across and over the edges of the carrier substrate to facilitate electrical connection to a circuit board. A lid is provided which is placed over the IC. A low-melting temperature adhesive means is then placed on the lid-to-carrier interface and is exposed to heat hermetically sealing the IC. A hermetically sealed carrier including a single silicon die which includes both an active region where an integrated circuit may be fabricated and an inactive region is also provided. Electrical leads are electrically interconnected to the IC of the active region and extend to the periphery of the inactive region of the silicon die. A lid and adhesive means is provided for hermetically sealing the IC of the active region.
    Type: Grant
    Filed: January 28, 1991
    Date of Patent: March 2, 1993
    Inventors: Melvin C. August, Diane M. Christie, Arthur J. Hebert, Eugene F. Neumann, Richard R. Steitz