Patents by Inventor Dianne L. Lacey
Dianne L. Lacey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8288237Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device.Type: GrantFiled: August 14, 2009Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael A. Gribelyuk, Dianne L. Lacey, Fenton R. Feeney, Katherine L. Saenger, Sufi Zafar
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Patent number: 8153514Abstract: The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: GrantFiled: August 7, 2008Date of Patent: April 10, 2012Assignee: International Business Machines CorporationInventors: Wanda Andreoni, Alessandro C. Callegari, Eduard A. Cartier, Alessandro Curioni, Christopher P. D'Emic, Evgeni Gousev, Michael A. Gribelyuk, Paul C. Jamison, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Carlo A. Pignedoli, Joseph F. Shepard, Jr., Sufi Zafar
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Patent number: 7667277Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device.Type: GrantFiled: January 13, 2005Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael A. Gribelyuk, Dianne L. Lacey, Fenton R. McFeely, Katherine L. Saenger, Sufi Zafar
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Publication number: 20100015790Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device.Type: ApplicationFiled: August 14, 2009Publication date: January 21, 2010Applicant: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael A. Gribelyuk, Dianne L. Lacey, Fenton R. McFeely, Katherine L. Saenger, Sufi Zafar
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Patent number: 7566938Abstract: A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.Type: GrantFiled: November 17, 2005Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Alessandro C. Callegari, Michael A. Gribelyuk, Paul C. Jamison, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Deborah A. Neumayer, Pushkar Ranade, Sufi Zafar
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Patent number: 7521346Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 ? classical), which cannot be achieved using TaSiN.Type: GrantFiled: October 19, 2007Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Martin M. Frank, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Sufi Zafar
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Publication number: 20080293259Abstract: The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: ApplicationFiled: August 7, 2008Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wanda Andreoni, Alessandro C. Callegari, Eduard A. Cartier, Alessandro Curioni, Christopher P. D'Emic, Evgeni Gousev, Michael A. Gribelyuk, Paul C. Jamison, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Carlo A. Pignedoli, Joseph F. Shepard, JR., Sufi Zafar
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Publication number: 20080245658Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/ interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 ? classical), which cannot be achieved using TaSiN.Type: ApplicationFiled: June 18, 2008Publication date: October 9, 2008Applicant: International Business Machines CorporationInventors: Alessandro C. Callegari, Martin M. Frank, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Sufi Zafar
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Patent number: 7115959Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: GrantFiled: June 22, 2004Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Wanda Andreoni, Alessandro C. Callegari, Eduard A. Cartier, Alessandro Curioni, Christopher P. D'Emic, Evengi Gousev, Michael A. Gribelyuk, Paul C. Jamison, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Carlo A. Pignedoli, Joseph P. Shepard, Jr., Sufi Zafar
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Patent number: 6982230Abstract: A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.Type: GrantFiled: November 8, 2002Date of Patent: January 3, 2006Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Alessandro C. Callegari, Michael A. Gribelyuk, Paul C. Jamison, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Deborah A. Neumayer, Pushkar Ranade, Sufi Zafar
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Patent number: 6798953Abstract: A structure that includes a substrate, typically a semiconductor chip such as a VCSEL or photodetector chip, and a guide for aligning a signal conveying device, typically an optical fiber, to a transducer such as an optoelectronic device on the semiconductor chip. The guide is formed, in a preferred embodiment, by lithographically exposing and developing a thick layer of photoresist. The structure is assembled by placing and securing the signal conveying device into a cavity-like region of the guide.Type: GrantFiled: January 7, 2000Date of Patent: September 28, 2004Assignee: International Business Machines CorporationInventors: Mitchell S. Cohen, Michael J. Cordes, Steven A. Cordes, William K. Hogan, Glen W. Johnson, Daniel M. Kuchta, Dianne L. Lacey, James L. Speidell, Jeannine M. Trewhella, Joseph P. Zinter
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Publication number: 20040092073Abstract: A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.Type: ApplicationFiled: November 8, 2002Publication date: May 13, 2004Inventors: Cyril Cabral, Alessandro C. Callegari, Michael A. Gribelyuk, Paul C. Jamison, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Deborah A. Neumayer, Pushkar Ranade, Sufi Zafar
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Patent number: 6573197Abstract: The present invention provides a method of fabricating a thermally stable polysilicon/high-k dielectric film stack utilizing a deposition method wherein Si-containing precursor gas which includes silicon and hydrogen is diluted with an inert gas such as He so as to significantly reduce the hydrogen content in the resultant polysilicon film. Semiconductor structures such as field effect transistors (FETs) and capacitors which include at least the thermally stable polysilicon/high-k dielectric film stack are also provided herein.Type: GrantFiled: April 12, 2001Date of Patent: June 3, 2003Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Evgeni Gousev, Michael A. Gribelyuk, Paul C. Jamison, Dianne L. Lacey
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Publication number: 20020151142Abstract: The present invention provides a method of fabricating a thermally stable polysilicon/high-k dielectric film stack utilizing a deposition method wherein Si-containing precursor gas which includes silicon and hydrogen is diluted with an inert gas such as He so as to significantly reduce the hydrogen content in the resultant polysilicon film. Semiconductor structures such as field effect transistors (FETs) and capacitors which include at least the thermally stable polysilicon/high-k dielectric film stack are also provided herein.Type: ApplicationFiled: April 12, 2001Publication date: October 17, 2002Inventors: Alessandro C. Callegari, Evgeni Gousev, Michael A. Gribelyuk, Paul C. Jamison, Dianne L. Lacey
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Patent number: 4859253Abstract: A method for passivating the surface of a compound semiconductor comprises annealing the substrate to form an anion rich surface layer containing cationic and anionic oxides and stripping the oxides to leave only a very thin anionic layer on the surface. The substrate is then subjected to an H.sub.2 plasma cleaning to remove chemisorbed oxygen. An N.sub.2 plasma cleaning is then performed to form an anionic nitride layer that is free of any cationic nitride. A layer of insulating material, such as, a native or other oxide, or a nitride, is deposited. The resulting structure has a very low interface state density such that the Fermi level may be swept through the entire band gap.Type: GrantFiled: July 20, 1988Date of Patent: August 22, 1989Assignee: International Business Machines CorporationInventors: Douglas A. Buchanan, Alessandro C. Callegari, Peter D. Hob, Dianne L. Lacey
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Patent number: 4853346Abstract: A method for forming an ohmic contact on a GaAs semiconductor material comprising depositing a non-uniform layer of Au onto the surface layer of the semiconductor material, depositing a multi-layer ohmic contact of AuGeNi onto the non-uniform layer and alloying the ohmic contact to the semiconductor material. The non-uniform Au layer may be deposited by backscattering Au during sputter cleaning of the semiconductor surface wherein the electrode is coated with Au. After alloying, the ohmic contact comprises a two layer structure having a high density of large area NiAs(Ge) grains contacting the semiconductor material as the first layer and an AuGa phase as the top layer. The ohmic contact has reduced contact resistance and exhibits a reduction in the spread of contact resistance after high temperature annealing.Type: GrantFiled: December 31, 1987Date of Patent: August 1, 1989Assignee: International Business Machines CorporationInventors: John M. Baker, Alessandro C. Callegari, Dianne L. Lacey, Yih-Cheng Shih