Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.

Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.

Abstract: A chip is provided, which includes a first receiving module, a protocol logic module, a color space conversion module, a compression module and a transmitting module. The first receiving module is configured to receive a digital video signal. The protocol logic module is configured to perform protocol unpacking on the digital video signal to obtain a video code stream. The color space conversion module is configured to perform color space conversion on the video code stream. The compression module is configured to perform lossless compression on the video code stream obtained by the color space conversion. The transmitting module is configured to transmit the video code stream obtained by the lossless compression.

Abstract: A clock and data recovery circuit and a phase interpolator therefor are provided. The clock and data recovery circuit includes a phase-locked loop, a control unit and the phase interpolator, a receiving circuit, a serial-to-parallel conversion circuit. The phase interpolator is connected with the control unit of the clock and data recovery circuit, and the phase interpolator includes: an encoding circuit, two multiplexers, a clock mixer, and two differential to single-ended amplifiers. The control unit is configured to further control the encoding circuit to change a delay position for a clock outputted by the phase interpolator in a case that the data sampled in the current clock position is not the optimal sampled data, to lead or lag the clock, thereby forming a stable state in which the clock follows the data dynamically.

Abstract: A clock and data recovery circuit and a phase interpolator therefor are provided. The clock and data recovery circuit includes a phase-locked loop, a control unit and the phase interpolator, a receiving circuit, a serial-to-parallel conversion circuit. The phase interpolator is connected with the control unit of the clock and data recovery circuit, and the phase interpolator includes: an encoding circuit, two multiplexers, a clock mixer, and two differential to single-ended amplifiers. The control unit is configured to further control the encoding circuit to change a delay position for a clock outputted by the phase interpolator in a case that the data sampled in the current clock position is not the optimal sampled data, to lead or lag the clock, thereby forming a stable state in which the clock follows the data dynamically.

Abstract: A process for cleaning a compound semiconductor wafer; the compound semiconductor wafer comprises, taking gallium arsenide (GaAs) as a representative, a group III-V compound semiconductor wafer. The process comprises the following steps: 1) treating the wafer with a mixture of dilute ammonia, hydrogen peroxide and water at a temperature not higher than 20° C.; 2) washing the wafer with deionized water; 3) treating the wafer with an oxidant; 4) washing the wafer with deionized water; 5) treating the wafer with a dilute acid solution or a dilute alkali solution; 6) washing the wafer with deionized water; and 7) drying the resulting wafer. The process can improve the cleanliness, micro-roughness and uniformity of the wafer surface.

Abstract: A process for cleaning a compound semiconductor wafer; the compound semiconductor wafer comprises, taking gallium arsenide (GaAs) as a representative, a group III-V compound semiconductor wafer. The process comprises the following steps: 1) treating the wafer with a mixture of dilute ammonia, hydrogen peroxide and water at a temperature not higher than 20° C.; 2) washing the wafer with deionized water; 3) treating the wafer with an oxidant; 4) washing the wafer with deionized water; 5) treating the wafer with a dilute acid solution or a dilute alkali solution; 6) washing the wafer with deionized water; and 7) drying the resulting wafer. The process can improve the cleanliness, micro-roughness and uniformity of the wafer surface.