Patents by Inventor Diarmuid McSwiney

Diarmuid McSwiney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8391415
    Abstract: An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: March 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul Kelleher, Diarmuid McSwiney, Conor O'Keeffe
  • Patent number: 8306172
    Abstract: A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: November 6, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul Kelleher, Diarmuid McSwiney, Conor O'Keeffe, Emilio Quiroga, Samir Soni
  • Publication number: 20110142169
    Abstract: An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.
    Type: Application
    Filed: January 9, 2007
    Publication date: June 16, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Paul Kelleher, Diarmuid McSwiney, Conor O'keeffe
  • Publication number: 20100111154
    Abstract: A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.
    Type: Application
    Filed: January 9, 2007
    Publication date: May 6, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Paul Kelleher, Diarmuid McSwiney, Conor O'Keeffe, Emilio Quiroga, Samir Soni
  • Publication number: 20100048239
    Abstract: A communication device is capable of supporting communication compliant with a Dual-Mode 2.5G and 3G interface baseband-radio frequency interface standard and comprises a data interface operably coupled to a number sub-systems and a clock circuit generating a plurality of clock phases for supporting communication there between. At least one of the number of sub-systems comprises a line driver and a line receiver; wherein the communication device is characterised in that the line receiver determines an end of a received data frame sent across the data interface and in response thereto switches itself off.
    Type: Application
    Filed: January 11, 2007
    Publication date: February 25, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Paul Kelleher, Patrick Gayer, Diarmuid McSwiney
  • Publication number: 20080195920
    Abstract: A digital interface (22) includes a self-test structure (56). The structure (56) includes a transmit section (52) and a receive section (36) having a correlator (68). A method (114) of testing the interface (22) entails coupling the receive section (36) with the transmit section (52) and communicating a test data structure (86) from the transmit section (52) to the receive section (36) at a high data rate. The test data structure (86) includes a pre-defined sync pattern (88), a header (90), and a payload (92). The receive section (36) detects the sync pattern (88) and performs time frame synchronization (148) at the correlator (68). When synchronization (148) is successful, the receive section (36) decodes (154, 162) the header (90) and the payload (92). If time frame synchronization (148) and decoding (154, 162) are successful, a validation indicator (100) is output for external observation at a low data rate.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 14, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lawrence B. Luce, Paul Kelleher, Diarmuid McSwiney