Abstract: A structure of protection of an area of a semiconductor wafer including a lightly-doped substrate of a first conductivity type against high-frequency noise likely to be injected from components formed in the upper portion of a second area of the wafer. The structure includes a very heavily-doped wall of the first conductivity type having substantially the depth of the upper portion. The wall is divided into segments, each of which is connected to a ground plane.

Abstract: An amplifier circuit including at least one first input amplifier; at least one second amplifier cascode-assembled with the first amplifier; and at least one reactive impedance circuit, mounted in series with the second amplifier, the reactive impedance circuit being formed by two impedances respectively exhibiting a maximum value for a first and a second frequency, to form a double-band amplifier circuit.

Abstract: The amplifier includes an input amplifier stage, an output amplifier stage cascode-connected with the input amplifier stage, and a load stage connected to the output stage. The load stage includes a plurality of circuits each including a capacitive component and an inductive component having a Q greater than 10, and having respective different resonant frequencies. All the gain curves respectively associated with all the circuits have, to within a stated tolerance, the same maximum gain value at the resonant frequencies. The gain curves respectively associated with two circuits having respective immediately adjacent resonant frequencies overlap below a threshold 3 dB, to within a stated tolerance, below the maximum gain value.

Abstract: A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a substrate-on-insulator type semiconductor substrate having a lower portion on top of which there is an upper insulating layer. A first semiconductor block and a second semiconductor block are produced in the upper insulating layer, and decoupling means are arranged in the upper insulating layer between the first and second semiconductor blocks. The first semiconductor block defines a first capacitor with the lower portion of the substrate, the second semiconductor block defines a second capacitor with the lower portion of the substrate, and the decoupling means includes at least one semiconductor well that defines a decoupling capacitor with the lower portion of the substrate. The capacitance of the decoupling capacitor is higher than the capacitance of each of the first and second capacitors.

Abstract: A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a semiconductor substrate having a lower portion on top of which there is an upper layer that is more heavily doped than the lower portion. A first block and a second block are produced in the upper part of the substrate, and decoupling means are arranged in the vicinity of the first block. The decoupling means include at least one decoupling circuit that is connected to the lower portion of the substrate and to a ground connection pad, and the decoupling circuit has a minimum impedance at a predetermined frequency. In one preferred embodiment, the decoupling circuit includes an inductive-capacitive resonant circuit having a resonant frequency substantially equal to the predetermined frequency.

Abstract: The present invention relates to a circuit of reception of bits transmitted on an asynchronous signal, including a circuit for providing a clock reconstructed from the asynchronous signal, this clock being used to sample the asynchronous signal to form a synchronous output signal, and a reception error detection circuit. The reception error detection circuit includes an edge detector providing a detection pulse for each edge of predetermined direction of the asynchronous signal; and an alarm circuit activating an alarm signal when an edge of predetermined direction of the synchronous signal occurs outside a detection pulse.

Abstract: A circuit for transmitting data in asynchronous transfer mode includes two phase-locked loops associated with a transmission unit and a reception unit, respectively. Each PLL is provided with a voltage-controlled oscillator formed by an astable multivibrator. The reference current fixing the free oscillating frequency of the multivibrator that is associated with the reception unit corresponds to the frequency adjustment current of the multivibrator that is associated with the transmission unit. Each VCO includes a differential amplifier, connected as a voltage-to-current converter, receiving two voltages corresponding to the phase error of the loop with which it is associated, and providing a frequency adjustment current of its astable multivibrator.

Abstract: An ECL stage has its current consumption adapted to its operation speed. For this purpose, the load resistor and the bias current source are adjustable so that the product of the current value of the source by the resistor value is substantially constant.

Abstract: A device for serializing binary data includes at least one first multiplexer controlled by a first sampling signal. The first sampling signal is provided by a divider of a phase-locked loop providing a transmission clock signal for serialized data based on a first clock signal of parallel data. The serialization device includes, up-stream from the first multiplexer, a shift register for conferring to the parallel data a delay substantially corresponding to a phase shift between the first clock signal and the first sampling signal.

Abstract: A voltage regulator controls at least one current source of at least one coupled-mode logic gate. The voltage regulator includes a first current source, of a bipolar-type, connected between ground and a first resistor that is connected to a supply voltage. The first current source is controlled by a voltage across a second resistor that is fed by a current from a second current source of a MOS-type. The current value of the second source determines the voltage of an output terminal of the regulator by duplicating this current on a third current source that is mirror-connected to the second source.

Abstract: A logic circuit has at least one first differential stage made of bipolar transistors operating in linear mode. The first differential stage is connected in a branch of a second differential stage biased by a current source. The second stage and the current source are made of MOS transistors.