Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.

Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

Abstract: An electronic system implements a software application described in the form of a graph of the Kahn network type, and includes actors. At least one of the actors includes a processor, and at least another one of the actors includes a hardware accelerator. Buffer memories are coupled between the actors. A central processor is configured to enable communications between the actors according to a communications and synchronization protocol. The processor and the hardware accelerator are configured to use different individual communications protocols.

Abstract: An electronic system implements a software application described in the form of a graph of the Kahn network type, and includes actors. At least one of the actors includes a processor, and at least another one of the actors includes a hardware accelerator. Buffer memories are coupled between the actors. A central processor is configured to enable communications between the actors according to a communications and synchronization protocol. The processor and the hardware accelerator are configured to use different individual communications protocols.

Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits. A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.

Abstract: An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising steps consisting of decomposing the executable code into words; compressing each word of executable code, each compressed word of executable code comprising a part of predefined fixed length and a part of variable length whereof the length is defined by the part of fixed length; and combining all the parts of fixed length and all the parts of variable length of the words respectively into a block of parts of fixed length and in a block of parts of variable length, the respective positions of at least certain parts of variable length in the block of parts of variable length being saved in an addressing table.

Abstract: An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising decomposing the executable code into words; dividing the executable code into instruction lines; compressing each word of each line in the form of a compressed word of variable length, the compressed words of a line being combined into a line of compressed words; and constituting an addressing table localizing each of the lines of compressed words in a block of lines compressed words and comprising one input per group of lines of compressed words, each input (j) specifying the position of a first line of compressed words in the block, and the respective lengths of the lines of compressed words of group, except for a last line of compressed words of the group, whereof the length is determined by means of the position of a first line of compressed words of a following group.

Abstract: The invention relates to a process for compression of executable code (2) by a microprocessor, comprising steps consisting of decomposing the executable code into words; compressing each word of executable code, each compressed word of executable code comprising a part (BC) of predefined fixed length and a part (VLI) of variable length whereof the length is defined by the part of fixed length; and combining all the parts of fixed length and all the parts of variable length of the words respectively into a block of parts of fixed length and in a block (12) of parts of variable length, the respective positions of at least certain parts of variable length in the block of parts of variable length being saved in an addressing table (13).

Abstract: An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising decomposing the executable code into words; dividing the executable code into instruction lines; compressing each word of each line in the form of a compressed word of variable length, the compressed words of a line being combined into a line of compressed words; and constituting an addressing table localizing each of the lines of compressed words in a block of lines compressed words and comprising one input per group of lines of compressed words, each input (j) specifying the position of a first line of compressed words in the block, and the respective lengths of the lines of compressed words of group, except for a last line of compressed words of the group, whereof the length is determined by means of the position of a first line of compressed words of a following group.

Abstract: The present invention relates to a data processing system comprising a processor provided with two memory access units operating in parallel; two separate memories respectively associated with the two access units; and circuitry for, when the address of a datum to be written into a memory is in a predetermined address range, writing the datum into both memories at the same time at the same address.

Abstract: The present invention relates to a processor including at least one memory access unit for presenting a read or write address over an address bus of a memory in response to the execution of a read or write instruction; and an arithmetic and logic unit operating in parallel with the memory access unit and arranged at least to present data on the data bus of the memory while the memory access unit presents a write address. The processor includes a write address queue in which is stored each write address provided by the memory access unit waiting for the availability of the data to be written.

Abstract: A process is for determining an overflow to the format of the result of an arithmetic operation carried out by an arithmetic unit on two operands A and B and an input carry digit Cin. This process is executed in parallel to the processing done by the AU on operands A and B, before the AU has determined the result S of the operation.