Abstract: A method is for rejecting spurs within a chip containing analog and digital functions. The spurs may be timed by a clock signal derived from the output frequency of a high frequency phase locked loop. Original analog rejection bandwidths associated with operation of analog functions may be determined, and then original spurs associated with operation of the digital functions and capable of directly or indirectly affecting the original analog rejection bandwidths may be identified. A final analog rejection bandwidth may be determined based on the original analog rejection bandwidths, and final spurs may be obtained based on the original spurs. A frequency shift of the output frequency of the high frequency phase locked loop to effectuate a rejection of the final spurs from the final analog rejection bandwidth may be determined, and the high frequency phase locked loop may be controlled to shift the output frequency by the frequency shift.

Abstract: A mobile telephony radiocommunication management process, with first time slots and second time slots being provided independently of each other, said process comprising the default selection of first time slots for transmitting/receiving first bursts corresponding to these first time slots, and in the case of a first time slot at least partially overlapping with a second time slot, choosing the first time slot or the second time slot, for respectively transmitting/receiving the first burst corresponding to the first time slot or receiving the second burst corresponding to the second time slot, with this choice being made so as to minimize the number of second bursts received for a given result.

Abstract: There is described a method for optimizing block reception for products that do support a simultaneous use of at least two SIM cards.

Abstract: A method is for rejecting spurs within a chip containing analog and digital functions. The spurs may be timed by a clock signal derived from the output frequency of a high frequency phase locked loop. Original analog rejection bandwidths associated with operation of analog functions may be determined, and then original spurs associated with operation of the digital functions and capable of directly or indirectly affecting the original analog rejection bandwidths may be identified. A final analog rejection bandwidth may be determined based on the original analog rejection bandwidths, and final spurs may be obtained based on the original spurs. A frequency shift of the output frequency of the high frequency phase locked loop to effectuate a rejection of the final spurs from the final analog rejection bandwidth may be determined, and the high frequency phase locked loop may be controlled to shift the output frequency by the frequency shift.

Abstract: There is described a method for optimizing block reception for products that do support a simultaneous use of at least two SIM cards.

Abstract: A mobile telephony radiocommunication management process, with first time slots and second time slots being provided independently of each other, said process comprising the default selection of first time slots for transmitting/receiving first bursts corresponding to these first time slots, and in the case of a first time slot at least partially overlapping with a second time slot, choosing the first time slot or the second time slot, for respectively transmitting/receiving the first burst corresponding to the first time slot or receiving the second burst corresponding to the second time slot, with this choice being made so as to minimize the number of second bursts received for a given result.

Abstract: A methodology for acquiring a frequency correction burst using a radio communication device including an RF circuit and digital processing circuitry is disclosed. The radio communication device employs a time period during which an signal acquisition time window is open and during which the RF circuit is activated to receive RF signals intended to be processed by the digital processing circuitry. The acquisition time window is discontinuous and includes N sub-acquisition windows during which the RF circuit is activated, wherein N?2. The N sub-acquisition windows are separated from one another by N?1 non-acquisition time slots, during which the RF circuit is deactivated. In one embodiment, a portion of the digital processing circuitry is deactivated during those times when the RF circuit is activated.

Abstract: A methodology for acquiring a frequency correction burst using a radio communication device including an RF circuit and digital processing circuitry is disclosed. The radio communication device employs a time period during which an signal acquisition time window is open and during which the RF circuit is activated to receive RF signals intended to be processed by the digital processing circuitry. The acquisition time window is discontinuous and includes N sub-acquisition windows during which the RF circuit is activated, wherein N?2. The N sub-acquisition windows are separated from one another by N?1 non-acquisition time slots, during which the RF circuit is deactivated. In one embodiment, a portion of the digital processing circuitry is deactivated during those times when the RF circuit is activated.

Abstract: An improved Integrated Circuit (IC) device is delineated comprising, in combination, an IC including an embedded Digital Signal Processor (DSP), an embedded Random Access Memory (RAM), an embedded Read Only Memory (ROM) having at least one portion thereof which is flawed and embedded patching circuitry having as inputs the current DSP program address and at least one break address wherein each break address corresponds to a separate flawed portion of the embedded ROM. The patching circuitry supplies data stored in flawless portions of the ROM to the DSP until the current DSP program address matches a break address indicating that the next portion of the embedded ROM is flawed. In place of the data stored in the flawed portion of the embedded ROM, the patching circuitry supplies corrected data stored in the embedded RAM to the DSP, and after this corrected data is supplied, data transfer to the DSP from the remaining unflawed portions of the embedded ROM is resumed.