Abstract: An image sensor includes a plurality of pixels each including a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor, the first capacitive node being linked to the readout node by a third transistor, and the readout node being linked to a node for applying a reset potential by a fourth transistor.

Abstract: An image sensor includes a plurality of pixels each including a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor, the first capacitive node being linked to the readout node by a third transistor, and the readout node being linked to a node for applying a reset potential by a fourth transistor.

Abstract: An image sensor including a pixel assembly, each pixel including a photodiode and an access transistor connected to a read circuit, the photodiode and the access transistor being formed in and above a first semiconductor substrate, all or part of the read circuit being formed in a second semiconductor substrate, the second substrate being placed above the first substrate and separated therefrom by an intermediary insulating layer covering the access transistor, the photodiode receiving incident photons on its lower surface side opposite to the intermediary insulating layer.

Abstract: A method for controlling a photosensitive cell including a photodiode connected to a read node via a MOS transfer transistor, the read node being connected to a source of a reference voltage via a MOS reset transistor, cyclically including a waiting phase at the end of which the photodiode is isolated from the reference voltage; an integration phase during which the voltage of the photodiode varies from a reset voltage to a useful voltage that depends on the lighting; and a phase of reading a voltage representative of the useful voltage, wherein the isolation of the photodiode of the read node at the end of the waiting phase includes the steps of setting the transfer transistor to the on state, the reset transistor being off; turning off the transfer transistor; and setting the reset transistor to the on state.

Abstract: An image sensor including a pixel assembly, each pixel including a photodiode and an access transistor connected to a read circuit, the photodiode and the access transistor being formed in and above a first semiconductor substrate, all or part of the read circuit being formed in a second semiconductor substrate, the second substrate being placed above the first substrate and separated therefrom by an intermediary insulating layer covering the access transistor, the photodiode receiving incident photons on its lower surface side opposite to the intermediary insulating layer.

Abstract: A method for controlling a photosensitive cell including a photodiode connected to a read node via a MOS transfer transistor, the read node being connected to a source of a reference voltage via a MOS reset transistor, cyclically including a waiting phase at the end of which the photodiode is isolated from the reference voltage; an integration phase during which the voltage of the photodiode varies from a reset voltage to a useful voltage that depends on the lighting; and a phase of reading a voltage representative of the useful voltage, wherein the isolation of the photodiode of the read node at the end of the waiting phase includes the steps of setting the transfer transistor to the on state, the reset transistor being off; turning off the transfer transistor; and setting the reset transistor to the on state.

Abstract: A charge transfer memory and its fabrication method are disclosed. The memory has charge transfer shift registers, with four phases and two level of electrodes, and a reading register with two phases and three levels of electrodes. At one end of each shift register, there is a final electrode contiguous with a reading storage electrode of the reading register, which is itself contiguous to a reading transfer electrode. These electrodes are made in a layer, with a second type of doping, of a semiconductor substrate with a first type of doping. Zones with a third type of doping are made facing the transfer electrodes of the reading register. According to the invention, facing the final electrode of each shift register, a zone with a fourth type of doping is made. This zone with a fourth type of doping prevents charges flowing in the reading register from returning to a shift register.

Abstract: Disclosed are a charge-coupled device with lowering of output potential as well as a method for the fabrication of this device. In a known way, the device comprises, upstream on a semiconducting substrate with a first type of doping (P), a semiconducting layer with a second type of doping (N) and an insulating layer covering the former layer. Pairs of electrodes are formed on the insulating layer. Each pair has a transfer electrode and a storage electrode. Zones with a third type of doping N.sup.+) are made in the layer of a second type (N). A layer with a third type of doping (N.sup.-) is made downstream, in the layer with a second type of doping, and, downstream, there is formed at least one other pair of additional transfer and storage electrodes. A zone with a fourth type of doping (N.sup.--) is made beneath the additional transfer electrode in the layer with a third type of doping (N.sup.-).