Patents by Inventor Didier Malcavet

Didier Malcavet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220240590
    Abstract: This electronic cigarette (1) comprises: —a heating element (10) able to vapourize a substrate during a smoking period; —means (30) for measuring an approximation (AUIOMESOO, UIOMESOO) of a characteristic of the voltage (U10(t)) across the terminals of the heating element (10) during this smoking period, said approximation being measured across the terminals (BI, B2) of a circuit (500) no component of which exhibits intrinsic characteristics not disturbed by the inhalations; —means (30) of estimating an approximation (AU10TH(t), UIO-m(t)) of said characteristic of the voltage (U10(t)) across the terminals of the heating element (10) in the absence of inhalation during said smoking period; means (30) of calculating an intensity (F) representative of the intensity of the inhalations during said smoking period on the basis of an integration of the difference between said approximations during said smoking period; and —means (30) of estimating the said quantity of substrate vapourized by the heating element at le
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Applicant: JT International S.A.
    Inventors: Eric Louveau, Didier Malcavet, Steve Anavi, Alexandre Prot
  • Patent number: 11350670
    Abstract: This electronic cigarette (1) comprises: —a heating element (10) able to vapourize a substrate during a smoking period; —means (30) for measuring an approximation (AUIOMESOO, UIOMESOO) of a characteristic of the voltage (U10(t)) across the terminals of the heating element (10) during this smoking period, said approximation being measured across the terminals (BI, B2) of a circuit (500) no component of which exhibits intrinsic characteristics not disturbed by the inhalations; —means (30) of estimating an approximation (AU10TH(t), UIO-m(t)) of said characteristic of the voltage (U10(t)) across the terminals of the heating element (10) in the absence of inhalation during said smoking period; means (30) of calculating an intensity (F) representative of the intensity of the inhalations during said smoking period on the basis of an integration of the difference between said approximations during said smoking period; and —means (30) of estimating the said quantity of substrate vapourized by the heating element at le
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 7, 2022
    Inventors: Eric Louveau, Didier Malcavet, Steve Anavi, Alexandre Prot
  • Publication number: 20190342948
    Abstract: This electronic cigarette (1) comprises: —a heating element (10) able to vapourize a substrate during a smoking period; —means (30) for measuring an approximation (AUIOMESOO, UIOMESOO) of a characteristic of the voltage (U10(t)) across the terminals of the heating element (10) during this smoking period, said approximation being measured across the terminals (BI, B2) of a circuit (500) no component of which exhibits intrinsic characteristics not disturbed by the inhalations; —means (30) of estimating an approximation (AU10TH(t), UIO-m(t)) of said characteristic of the voltage (U10(t)) across the terminals of the heating element (10) in the absence of inhalation during said smoking period; means (30) of calculating an intensity (F) representative of the intensity of the inhalations during said smoking period on the basis of an integration of the difference between said approximations during said smoking period; and —means (30) of estimating the said quantity of substrate vapourized by the heating element at le
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Applicant: JT International S.A.
    Inventors: Eric Louveau, Didier Malcavet, Steve Anavi, Alexandre Prot
  • Patent number: 10383174
    Abstract: This electronic cigarette comprises: —a heating element able to vaporize a substrate during a smoking period; —means for measuring an approximation of a characteristic of the voltage across the terminals of the heating element during this smoking period, said approximation being measured across the terminals of a circuit no component of which exhibits intrinsic characteristics not disturbed by the inhalations; —means of estimating an approximation of said characteristic of the voltage across the terminals of the heating element in the absence of inhalation during said smoking period; means of calculating an intensity representative of the intensity of the inhalations during said smoking period on the basis of an integration of the difference between said approximations during said smoking period; and —means of estimating the said quantity of substrate vaporized by the heating element at least on the basis of said intensity.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: August 13, 2019
    Inventors: Eric Louveau, Didier Malcavet, Steve Anavi, Alexandre Prot
  • Publication number: 20170019951
    Abstract: This electronic cigarette comprises: —a heating element able to vapourize a substrate during a smoking period; —means for measuring an approximation of a characteristic of the voltage across the terminals of the heating element during this smoking period, said approximation being measured across the terminals of a circuit no component of which exhibits intrinsic characteristics not disturbed by the inhalations; —means of estimating an approximation of said characteristic of the voltage across the terminals of the heating element in the absence of inhalation during said smoking period; means of calculating an intensity representative of the intensity of the inhalations during said smoking period on the basis of an integration of the difference between said approximations during said smoking period; and—means of estimating the said quantity of substrate vapourized by the heating element at least on the basis of said intensity.
    Type: Application
    Filed: February 20, 2015
    Publication date: January 19, 2017
    Applicant: JT International S.A.
    Inventors: Eric LOUVEAU, Didier MALCAVET, Steve ANAVI, Alexandre PROT
  • Patent number: 7661039
    Abstract: A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gerard Boudon, Didier Malcavet, David Pereira, Andre Steimle
  • Publication number: 20090019326
    Abstract: A self-synchronizing data bus analyser is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.
    Type: Application
    Filed: May 21, 2008
    Publication date: January 15, 2009
    Inventors: Gerard Boudon, Didier Malcavet, David Pereira, Andre Steimle
  • Patent number: 7474716
    Abstract: A data recovery circuit employing an oversampling technique. The incoming serial data stream with jitter is oversampled by means of the multiple phases of a reference clock to produce data samples. Each sample is compared to the samples collected with the next clock phase in an edge detector circuit to determine the presence of a data edge. The edge information, representative of the data edge positions, is stored and accumulated in the form of a bit map. A detection/suppression circuit detects and suppresses edges which are not adjacent to any other edge in the edge memory. A selection determination circuit uses the edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Vincent Vallet, Didier Malcavet
  • Patent number: 7404115
    Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: July 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Gerard Boudon, Didier Malcavet, David Pereira, Andre Steimle
  • Publication number: 20070011534
    Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.
    Type: Application
    Filed: December 1, 2005
    Publication date: January 11, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerard Boudon, Didier Malcavet, David Pereira, Andre Steimle
  • Publication number: 20060008040
    Abstract: A data recovery circuit employing an oversampling technique. The incoming serial data stream with jitter is oversampled by means of the multiple phases of a reference clock to produce data samples. Each sample is compared to the samples collected with the next clock phase in an edge detector circuit to determine the presence of a data edge. The edge information, representative of the data edge positions, is stored and accumulated in the form of a bit map. A detection/suppression circuit detects and suppresses edges which are not adjacent to any other edge in the edge memory. A selection determination circuit uses the edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 12, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vincent Vallet, Didier Malcavet
  • Publication number: 20040123004
    Abstract: There is described an improved FIFO based controller (12) for controlling the transfer of data from a CPU, typically a microprocessor, to a slave device (e.g. a SRAM) attached thereto to perform the management of tasks (or transactions). To improve performance, parallel access to the FIFO has been implemented in order to process pipe lined tasks in a shortened time. A task consists of an address (Address) and its associated qualifying bits (ST). The improved controller circuit (12) is comprised of four blocks: a task detection circuit (16), a FIFO controller (12), an innovative task management circuit (18) including the FIFO memory (19) and finally, a slave controller (20). The role of the task detection circuit is to detect valid tasks and inhibiting others. The FIFO controller generates signals to add new tasks in the FIFO memory (ADD TASK) and to clear tasks that have been executed when the data are available on the processor bus (CLEAR TASK).
    Type: Application
    Filed: November 7, 2003
    Publication date: June 24, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerard Boudon, Didier Malcavet