Patents by Inventor Didier Pinchon

Didier Pinchon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for determining at least one filter of a filter bank of a transmission or coding system, corresponding device and computer program
    Patent number: 9621394
    Abstract: A method is provided for determining at least one filter of a filter bank in a transmission or coding system, on the basis of a prototype filter p. The method includes determining coefficients p[k] of the prototype filter p, of length L equal to N, from ? angle parameters ?i, for 0?i???1, expressed on the basis of a polynomial function ƒ(x), also referred to as a compact representation, such that: f ? ( x ) = ? 4 + t ? ? k = 0 d - 1 ? ? ? k ? T 2 ? k ? ( t ) ; t = 2 ? x - 1.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 11, 2017
    Assignee: ORANGE
    Inventors: Pierre Siohan, Didier Pinchon
  • METHOD FOR DETERMINING AT LEAST ONE FILTER OF A FILTER BANK OF A TRANSMISSION OR CODING SYSTEM, CORRESPONDING DEVICE AND COMPUTER PROGRAM
    Publication number: 20150304144
    Abstract: A method is provided for determining at least one filter of a filter bank in a transmission or coding system, on the basis of a prototype filter p. The method includes determining coefficients p[k] of the prototype filter p, of length L equal to N, from ? angle parameters ?i, for 0?i???1, expressed on the basis of a polynomial function ƒ(x), also referred to as a compact representation, such that: f ? ( x ) = ? 4 + t ? ? k = 0 d - 1 ? ? ? k ? T 2 ? k ? ( t ) ; t = 2 ? x - 1.
    Type: Application
    Filed: November 19, 2013
    Publication date: October 22, 2015
    Inventors: Pierre Siohan, Didier Pinchon
  • Apparatus for argument reduction in exponential computations of IEEE standard floating-point numbers
    Patent number: 5463574
    Abstract: An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with .vertline.x.vertline.<1), determining the value of xi and computing (x-xi) according to the IEEE 754 standard floating-point format having a first circuit arrangement operative to perform pipeline operations on a N bit mantissa; the output of the first circuit arrangement being connected to a normalizer circuit of N+4 bits whose three left-most inputs are tied to "zero" and whose three left-most out bits J(0:2) are output on a three-bits bus (J-BUS).
    Type: Grant
    Filed: July 29, 1993
    Date of Patent: October 31, 1995
    Assignee: International Business Machines Corporation
    Inventors: Bernard Desrosiers, Didier Louis, Didier Pinchon, Andre Steimle
  • System for optimizing argument reduction
    Patent number: 5452241
    Abstract: A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system. A partial remainder operation is set forth for high accuracy reduction of polynomials whose arguments are greater than pi/4. The method may be practiced in a processor having a bus of approximately half the width of the precision of the desired result. Temporary registers are utilized for the storage of intermediate results. Full bus width accuracy is obtained through successive half bus width operations.
    Type: Grant
    Filed: March 14, 1994
    Date of Patent: September 19, 1995
    Assignee: International Business Machines Corporation
    Inventors: Bernard Desrosiers, Louis Didier, Didier Pinchon, Andre Steimle