Patents by Inventor Didier Pribat

Didier Pribat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10938026
    Abstract: The present invention provides a silicon nanowire structure embedded in nickel silicide nanowires for lithium-based battery anodes and anodes including the same. In particular, a Si nanowire structure embedded in NiSix nanowires according to the present invention may provide a solution to a problem, such as disconnection of Si nanowires from a current collector shown when the Si nanowires are expanded by alloying with Li or contracted during the use of a battery, and the like, by flexibly embedding the Si nanowires in the NiSix nanowires.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 2, 2021
    Assignees: Hyundai Motor Company, Research & Business Foundation Sungkyunkwan University, Kia Motors Corporation
    Inventors: Kyo Min Shin, Sa Heum Kim, Hong Seok Min, Mihai Robert Zamfir, Je Mee Joe, Didier Pribat, Yeo Jin Lee
  • Publication number: 20190273253
    Abstract: The present invention provides a silicon nanowire structure embedded in nickel silicide nanowires for lithium-based battery anodes and anodes including the same. In particular, a Si nanowire structure embedded in NiSix nanowires according to the present invention may provide a solution to a problem, such as disconnection of Si nanowires from a current collector shown when the Si nanowires are expanded by alloying with Li or contracted during the use of a battery, and the like, by flexibly embedding the Si nanowires in the NiSix nanowires.
    Type: Application
    Filed: May 1, 2019
    Publication date: September 5, 2019
    Inventors: Kyo Min Shin, Sa Heum Kim, Hong Seok Min, Mihai Robert Zamfir, Je Mee Joe, Didier Pribat, Yeo Jin Lee
  • Patent number: 10319995
    Abstract: The present invention provides a silicon nanowire structure embedded in nickel silicide nanowires for lithium-based battery anodes and anodes including the same. In particular, a Si nanowire structure embedded in NiSix nanowires according to the present invention may provide a solution to a problem, such as disconnection of Si nanowires from a current collector shown when the Si nanowires are expanded by alloying with Li or contracted during the use of a battery, and the like, by flexibly embedding the Si nanowires in the NiSix nanowires.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: June 11, 2019
    Assignees: Hyundai Motor Company, Research & Business Foundation Sungkyunkwan University
    Inventors: Kyo Min Shin, Sa Heum Kim, Hong Seok Min, Mihai Robert Zamfir, Je Mee Joe, Didier Pribat, Yeo Jin Lee
  • Patent number: 9206509
    Abstract: The invention includes a controlled graphene film growth process including the production on the surface of a substrate of a layer of a metal having with carbon a phase diagram such that, above a molar concentration threshold ratio CM/CM+CC, where CM is the molar metal concentration in a metal/carbon mixture and CC is the molar carbon concentration in the mixture, a homogeneous solid solution is obtained. The metal layer is exposed to a controlled flux of carbon atoms or carbon-containing radicals or carbon-containing ions at a temperature such that the molar concentration ratio obtained is greater than the threshold ratio to obtain a solid solution of carbon in the metal. The process further includes an operation for modifying the phase of the mixture into two phases, a metal phase and a graphite phase, leading to the formation of at least a lower graphene film at the metal layer incorporating carbon atoms-substrate interface and an upper graphene film at the surface of the metal layer.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: December 8, 2015
    Assignees: ECOLE POLYTECHNIQUE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Laurent Baraton, Costel Sorin Cojocaru, Didier Pribat
  • Publication number: 20150200391
    Abstract: The present invention provides a silicon nanowire structure embedded in nickel silicide nanowires for lithium-based battery anodes and anodes including the same. In particular, a Si nanowire structure embedded in NiSix nanowires according to the present invention may provide a solution to a problem, such as disconnection of Si nanowires from a current collector shown when the Si nanowires are expanded by alloying with Li or contracted during the use of a battery, and the like, by flexibly embedding the Si nanowires in the NiSix nanowires.
    Type: Application
    Filed: November 17, 2014
    Publication date: July 16, 2015
    Inventors: Kyo Min Shin, Sa Heum Kim, Hong Seok Min, Mihai Robert Zamfir, Je Mee Joe, Didier Pribat, Yeo Jin Lee
  • Patent number: 8138046
    Abstract: The invention relates to a process for fabricating a vertical transistor structure. On a substrate (10), is a first conductive layer (11), providing the source or drain electrode function, and an upper conductive layer (17), providing the drain or source electrode function. The production of a membrane includes a stack of porous layers including a first insulating layer (20), a second conductive layer (12), providing the gate electrode function, and an upper insulating layer (13?) on the surface of the substrate covered with the first conductive layer (11) providing the drain or source electrode function. The porous layers having substantially stacked pores. The production of filaments made of a semiconductor material is inside some of the stacked pores of the porous layers. The production of the upper conductive layer provides the source or drain electrode function on the surface of the stack of porous layers filled with filaments made of semiconductor material.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: March 20, 2012
    Assignee: Ecole Polytechnique
    Inventors: Didier Pribat, Costel-Sorin Cojocaru
  • Patent number: 8115198
    Abstract: In an array R of field-effect transistors for detecting analytes, each transistor of the array comprises a gate G, a semiconductor nanotube or nanowire element NT connected at one end to a source electrode S and at another end to a drain electrode D, in order to form, at each end, a junction J1, J2 with the channel. At least transistors FET1,1, FET1,2 of the array are differentiated by a different conducting material (m1, m2) of the source electrode S and/or drain electrode D.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: February 14, 2012
    Assignee: Thales and Ecole Polytechnique
    Inventors: Paolo Bondavalli, Pierre Legagneux, Pierre Le Barny, Didier Pribat, Julien Nagle
  • Patent number: 8008109
    Abstract: A method for manufacturing the active plate of a flat matrix display screen, in which each cell comprises an electrode plate connected by a transistor to a first conductive line, comprising the steps of providing an outgrowth coated with an insulator of each first conductive line at the level of each cell; etching or making porous an end portion of each outgrowth; laterally growing, for example, by a VLS method, a PIP or NIN semiconductor structure in each end portion which has been etched or made porous; and establishing a contact at the free end of the semiconductor structure and forming a gate at the level of the median portion of the semiconductor structure.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: August 30, 2011
    Assignees: Centre National de la Recherche Scientifique, Ecole Polytechnique
    Inventors: Didier Pribat, Costel Sorin Cojocaru
  • Publication number: 20110198313
    Abstract: The invention relates to a controlled graphene film growth process characterized in that it comprises the following steps: the production on the surface of a substrate (S1) of a layer of a metal having with carbon a phase diagram such that above a molar concentration threshold ratio CM/CM+CC, where CM is the molar metal concentration in a metal/carbon mixture and CC is the molar carbon concentration in said mixture, a homogeneous solid solution is obtained; the exposure of the metal layer to a controlled flux of carbon atoms or carbon-containing radicals or carbon-containing ions at a temperature such that the molar concentration ratio obtained is greater than the threshold ratio so as to obtain a solid solution of carbon in the metal; and an operation for modifying the phase of the mixture into two phases, a metal phase and a graphite phase respectively, leading to the formation of at least a lower graphene film (31) located at the (metal layer incorporating carbon atoms)/substrate interface and an upper
    Type: Application
    Filed: October 16, 2009
    Publication date: August 18, 2011
    Applicants: ECOLE POLYTECHNIQUE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Laurent Baraton, Costel-Sorin Cojocaru, Didier Pribat
  • Patent number: 7846819
    Abstract: A method of synthesizing electronic components incorporating nanoscale filamentary structures in which method a metallic catalyst is deposited in a nanoporous membrane , the catalyst being adapted to penetrate in at least some of the pores of the nanoporous membrane , and filamentary structures are grown on the catalyst in at least some of the pores in the nanoporous membrane . The nanoporous membrane is prepared in a manner suitable for ensuring that the wall of the pores include a single-crystal zone, and at least part of the catalyst is grown epitaxially on said single-crystal zone.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: December 7, 2010
    Assignees: Centre National de la Recherche Scientifique (CNRS), Ecole Polytechnique
    Inventors: Didier Pribat, Jean-Eric Wegrowe, Travis Wade
  • Publication number: 20100203686
    Abstract: A method for manufacturing the active plate of a flat matrix display screen, in which each cell comprises an electrode plate connected by a transistor to a first conductive line, comprising the steps of providing an outgrowth coated with an insulator of each first conductive line at the level of each cell; etching or making porous an end portion of each outgrowth; laterally growing, for example, by a VLS method, a PIP or NIN semiconductor structure in each end portion which has been etched or made porous; and establishing a contact at the free end of the semiconductor structure and forming a gate at the level of the median portion of the semiconductor structure.
    Type: Application
    Filed: June 29, 2006
    Publication date: August 12, 2010
    Inventors: Didier Pribat, Costel Sorin Cojocaru
  • Patent number: 7491269
    Abstract: The invention relates to a process for the growth of nanotubes or nanofibers on a substrate comprising at least an upper layer made of a first material, wherein: the formation, on the surface of the upper layer, of a barrier layer made of an alloy of the first material and of a second material, said alloy being stable at a first temperature; the formation of spots of catalyst that are made of the second material, on the surface of the alloy layer; and the growth of nanotubes or nanofibers at a second temperature below said first temperature. The alloy layer allows effective growth of nanotubes/nanofibers from catalyst spots on the surface of said alloy layer. This is because the alloy layer constitutes a diffusion barrier preventing the catalyst from diffusing into the growth substrate, which barrier is stable at the catalytic nanotube/nanofiber growth temperature.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: February 17, 2009
    Assignee: Thales
    Inventors: Pierre Legagneux, Didier Pribat, Yannig Nedellec
  • Publication number: 20090035908
    Abstract: The invention relates to a process for fabricating a vertical transistor structure. On a substrate (10), is a first conductive layer (11), providing the source or drain electrode function, and an upper conductive layer (17), providing the drain or source electrode function. The production of a membrane includes a stack of porous layers including a first insulating layer (20), a second conductive layer (12), providing the gate electrode function, and an upper insulating layer (13?) on the surface of the substrate covered with the first conductive layer (11) providing the drain or source electrode function. The porous layers having substantially stacked pores. The production of filaments made of a semiconductor material is inside some of the stacked pores of the porous layers. The production of the upper conductive layer provides the source or drain electrode function on the surface of the stack of porous layers filled with filaments made of semiconductor material.
    Type: Application
    Filed: February 5, 2007
    Publication date: February 5, 2009
    Applicant: Ecole Polytechnique
    Inventors: Didier Pribat, Costel-Sorin Cojocaru
  • Publication number: 20080210987
    Abstract: In an array R of field-effect transistors for detecting analytes, each transistor of the array comprises a gate G, a semiconductor nanotube or nanowire element NT connected at one end to a source electrode S and at another end to a drain electrode D, in order to form, at each end, a junction J1, J2 with the channel. At least transistors FET1,1, FET1,2 of the array are differentiated by a different conducting material (m1, m2) of the source electrode S and/or drain electrode D.
    Type: Application
    Filed: May 24, 2006
    Publication date: September 4, 2008
    Applicants: Thales, Ecole Polytechnique
    Inventors: Paolo Bondavalli, Pierre Legagneux, Pierre Le Barny, Didier Pribat, Julien Nagle
  • Patent number: 7214553
    Abstract: The invention relates to a process for the controlled growth of nanotubes or nanofibers on a substrate, characterized in that it furthermore comprises the production, on the substrate (11), of a bi-layer structure composed of a layer of catalyst material (71), for catalyzing the growth of nanotubes or nanofibers, and a layer of associated material, said associated material being such that it forms a noncatalytic alloy with the catalyst material at high temperature. The invention also relates to a process for fabricating a field-emission cathode using the above nanotube or nanofiber fabrication process. These processes allow very precise positioning of the catalyst spots from which the nanotubes and nanofibers can be grown and allow the fabrication of cathodes for which the nanotubes or nanofibers are self-aligned with the aperture in the extraction grid. Applications: electron tubes, nanolithography.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: May 8, 2007
    Assignee: Thales
    Inventors: Pierre Legagneux, Gilles Pirio, Didier Pribat, William Ireland Milne, Kenneth Boh Khin Teo
  • Publication number: 20060292870
    Abstract: A method of synthesizing electronic components incorporating nanoscale filamentary structures in which method a metallic catalyst is deposited in a nanoporous membrane, the catalyst being adapted to penetrate in at least some of the pores of the nanoporous membrane, and filamentary structures are grown on the catalyst in at least some of the pores in the nanoporous membrane. The nanoporous membrane is prepared in a manner suitable for ensuring that the wall of the pores include a single-crystal zone, and at least part of the catalyst is grown epitaxially on said single-crystal zone.
    Type: Application
    Filed: October 12, 2004
    Publication date: December 28, 2006
    Applicants: CENTRE NATIONAL DE LA RECHERCHE
    Inventor: Didier Pribat
  • Publication number: 20060280945
    Abstract: The invention provides a method of synthesizing a crystalline material in which seeds (6) are produced of a catalyst that is adapted to dissolve carbon on a substrate (2) of a first material; carbon nanotubes (6) are grown from the seeds (6); and a layer is produced of a second material comprising at least one monocrystalline region (12) orientated from a seed (6). The invention also provides the material obtained by said method. Application to the synthesis of polycrystalline silicon on a glass substrate.
    Type: Application
    Filed: June 25, 2004
    Publication date: December 14, 2006
    Inventor: Didier Pribat
  • Publication number: 20050235906
    Abstract: The invention relates to a process for the growth of nanotubes or nanofibers on a substrate comprising at least an upper layer made of a first material, wherein: the formation, on the surface of the upper layer, of a barrier layer made of an alloy of the first material and of a second material, said alloy being stable at a first temperature; the formation of spots of catalyst that are made of the second material, on the surface of the alloy layer; and the growth of nanotubes or nanofibers at a second temperature below said first temperature. The alloy layer allows effective growth of nanotubes/nanofibers from catalyst spots on the surface of said alloy layer. This is because the alloy layer constitutes a diffusion barrier preventing the catalyst from diffusing into the growth substrate, which barrier is stable at the catalytic nanotube/nanofiber growth temperature.
    Type: Application
    Filed: December 3, 2002
    Publication date: October 27, 2005
    Inventors: Pierre Legagneux, Didier Pribat, Yannig Nedellec, Pierre Legasneux, Didier Pribat, Yannig Nedellec
  • Publication number: 20040240157
    Abstract: The invention relates to a process for the controlled growth of nanotubes or nanofibers on a substrate, characterized in that it furthermore comprises the production, on the substrate (11), of a bi-layer structure composed of a layer of catalyst material (71), for catalyzing the growth of nanotubes or nanofibers, and a layer of associated material, said associated material being such that it forms a noncatalytic alloy with the catalyst material at high temperature.
    Type: Application
    Filed: March 19, 2004
    Publication date: December 2, 2004
    Inventors: Pierre Legagneux, Gilles Pirio, Didier Pribat, William Ireland Milne, Kenneth Boh Khin Teo
  • Patent number: 6476408
    Abstract: A field-emission device includes at least one plane cathode made of conductive material with a low electron affinity located on a face of a substrate carrying a layer of a dielectric material, which layer has at least one cavity in which the cathode is located. A gate made of conductive material is located on the dielectric layer and has an aperture centered with respect to the cavity. The conductive material with a low electron affinity is a material deposited in amorphous form. Such a device may find particular application to electron guns or display devices.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: November 5, 2002
    Assignee: Thomson-CSF
    Inventors: Pierre Legagneux, Didier Pribat