Patents by Inventor Didier Seropian

Didier Seropian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for generating a user interface for timing budget analysis of integrated circuit designs
    Patent number: 8745560
    Abstract: In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: June 3, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vivek Bhardwaj, Didier Seropian, Oleg Levitsky
  • User interface for timing budget analysis of integrated circuit designs
    Patent number: 8504978
    Abstract: In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: August 6, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vivek Bhardwaj, Didier Seropian, Oleg Levitsky