Patents by Inventor Diego Crupnicoff
Diego Crupnicoff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230379390Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Liran Liss, Yamin Friedman, Michael Kagan, Diego Crupnicoff, Idan Burstein, Matty Kadosh, Tzah Oved, Dror Goldenberg, Ron Yuval Efraim, Alexander Eli Rosenbaum, Aviad Yehezkel, Rabia Loulou
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Patent number: 11765237Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.Type: GrantFiled: April 20, 2022Date of Patent: September 19, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Liran Liss, Yamin Friedman, Michael Kagan, Diego Crupnicoff, Idan Burstein, Matty Kadosh, Tzah Oved, Dror Goldenberg, Ron Yuval Efraim, Alexander Eli Rosenbaum, Aviad Yehezkel, Rabia Loulou
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Patent number: 11622004Abstract: A method for communication includes receiving in a network device work requests posted by a host processor to perform a series of communication transactions, including at least a first transaction and a second transaction comprising first and second operations to be executed in a sequential order in response to corresponding first and work requests posted by the host processor. In response to the work requests, data packets are transmitted over a network from the network device to a destination node and corresponding responses are received from the destination node. Based on the received responses, completion of the first operations in the first transaction is reported from the network device to the host processor according to the sequential order, and completion of the second operation in the second transaction is reported from the network device to the host processor regardless of whether the first transaction has been completed.Type: GrantFiled: August 18, 2022Date of Patent: April 4, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Yamin Friedman, Idan Burstein, Ariel Shahar, Diego Crupnicoff, Roee Moyal
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Patent number: 11494189Abstract: Methods and system for processing data in a programmable processing pipeline are disclosed. In an embodiment, a method for processing packets in a programmable packet processing pipeline is disclosed. The method involves processing data corresponding to a packet through a match-action pipeline of a programmable packet processing pipeline, and diverting the processing of data corresponding to the packet from the match-action pipeline to a processor core for out-of-pipeline processing.Type: GrantFiled: February 21, 2020Date of Patent: November 8, 2022Assignee: Pensando Systems Inc.Inventors: Diego Crupnicoff, Michael B. Galles
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Patent number: 11252088Abstract: A method for managing network congestion is provided. The method comprises: receiving, at a receiver, a packet comprising a timestamp provided by a first clock of a sender; deriving, by the receiver, a latency value based at least in part on the timestamp provided by the first clock and a receipt time provided by a second clock of the receiver; determining a latency change by comparing the latency value with a previous latency value; and determining a state of network congestion based at least in part on the latency change.Type: GrantFiled: August 30, 2018Date of Patent: February 15, 2022Assignee: PENSANDO SYSTEMS INC.Inventors: Raja Rao Tadimeti, Vijay K. Chander, Diego Crupnicoff, Vishal Jain, Madhava Rao Cheethirala
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Publication number: 20210263744Abstract: Methods and system for processing data in a programmable processing pipeline are disclosed. In an embodiment, a method for processing packets in a programmable packet processing pipeline is disclosed. The method involves processing data corresponding to a packet through a match-action pipeline of a programmable packet processing pipeline, and diverting the processing of data corresponding to the packet from the match-action pipeline to a processor core for out-of-pipeline processing.Type: ApplicationFiled: February 21, 2020Publication date: August 26, 2021Inventors: Diego CRUPNICOFF, Michael B. GALLES
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Publication number: 20200336426Abstract: A method for managing network congestion is provided. The method comprises: receiving, at a receiver, a packet comprising a timestamp provided by a first clock of a sender; deriving, by the receiver, a latency value based at least in part on the timestamp provided by the first clock and a receipt time provided by a second clock of the receiver; determining a latency change by comparing the latency value with a previous latency value; and determining a state of network congestion based at least in part on the latency change.Type: ApplicationFiled: August 30, 2018Publication date: October 22, 2020Inventors: Raja Rao TADIMETI, Vijay K. CHANDER, Diego CRUPNICOFF, Vishal JAIN, Madhava Rao CHEETHIRALA
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Patent number: 10776272Abstract: A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.Type: GrantFiled: March 2, 2016Date of Patent: September 15, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Idan Burstein, Diego Crupnicoff, Shlomo Raikin, Michael Kagan
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Patent number: 10708219Abstract: A method for communication, includes routing unicast data packets among nodes in a network using respective Layer-3 addresses that are uniquely assigned to each of the nodes. Respective Layer-2 unicast addresses are assigned to the nodes in accordance with an algorithmic mapping of the respective Layer-3 addresses. The unicast data packets are forwarded within subnets of the network using the assigned Layer-2 addresses.Type: GrantFiled: November 20, 2016Date of Patent: July 7, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Zachy Haramaty, Diego Crupnicoff, Freddy Gabbay, Benny Koren, Amiad Marelli, Itamar Rabenstein, Ido Bukspan, Oded Zemer
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Patent number: 10552367Abstract: Communication apparatus includes a host interface, configured to be coupled to a host processor having a host memory, and a network interface, which is configured to receive over a network from a sending node data packets conveying operations for execution in a sequential order on a predefined queue pair (QP), including at least a first packet conveying a posted write operation and a second packet conveying a non-posted write operation. Packet processing circuitry is configured to execute the posted write operation in accordance with the sequential order so as to write first data to the host memory prior to the execution of any subsequent operations in the sequential order, and to execute the non-posted write operation so as to write second data to the host memory while allowing one or more of the subsequent operations in the sequential order to be executed prior to completion of writing the second data.Type: GrantFiled: July 26, 2017Date of Patent: February 4, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Idan Burstein, Diego Crupnicoff
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Patent number: 10430374Abstract: A method for data transfer includes transmitting a sequence of data packets, including at least a first packet and a second packet transmitted subsequently to the first packet, from a first computer over a network to a second computer in a single remote direct memory access (RDMA) data transfer transaction. Upon receipt of the second packet at the second computer without previously having received the first packet, a negative acknowledgment (NAK) packet is sent from the second computer over the network to the first computer, indicating that the first packet was not received. In response to the NAK packet, the first packet is retransmitted from the first computer to the second computer without retransmitting the second packet.Type: GrantFiled: June 29, 2016Date of Patent: October 1, 2019Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Adi Menachem, Ariel Shahar, Noam Bloch, Diego Crupnicoff, Michael Kagan
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Patent number: 10284383Abstract: A switch in a data network is configured to mediate data exchanges among network elements. The apparatus further includes a processor, which organizes the network elements into a hierarchical tree having a root node network element, vertex node network elements, and child node network elements that include leaf node network elements. The leaf node network elements are originate aggregation data and transmit the aggregation data to respective parent vertex node network elements. The vertex node network elements combine the aggregation data from at least a portion of the child node network elements, and transmit the combined aggregation data from the vertex node network elements to parent vertex node network elements. The root node network element is operative for initiating a reduction operation on the aggregation data.Type: GrantFiled: August 30, 2016Date of Patent: May 7, 2019Assignee: Mellanox Technologies, Ltd.Inventors: Gil Bloch, Diego Crupnicoff, Benny Koren, Oded Wertheim, Lion Levi, Richard Graham, Michael Kagan
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Patent number: 10237376Abstract: A method for congestion control includes receiving at a destination computer a packet transmitted on a given flow, in accordance with a predefined transport protocol, through a network by a transmitting network interface controller (NIC) of a source computer, and marked by an element in the network with a forward congestion notification. Upon receiving the marked packet in a receiving NIC of the destination computer, a congestion notification packet (CNP) indicating a flow to be throttled is immediately queued for transmission from the receiving NIC through the network to the source computer. Upon receiving the CNP in the transmitting NIC, transmission of further packets on at least the flow indicated by the CNP from the transmitting NIC to the network is immediately throttled, and an indication of the given flow is passed from the transmitting NIC to a protocol processing software stack running on the source computer.Type: GrantFiled: September 28, 2016Date of Patent: March 19, 2019Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Diego Crupnicoff, Michael Kagan, Noam Bloch, Adi Menachem, Idan Burstein
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Publication number: 20190034381Abstract: Communication apparatus includes a host interface, configured to be coupled to a host processor having a host memory, and a network interface, which is configured to receive over a network from a sending node data packets conveying operations for execution in a sequential order on a predefined queue pair (QP), including at least a first packet conveying a posted write operation and a second packet conveying a non-posted write operation. Packet processing circuitry is configured to execute the posted write operation in accordance with the sequential order so as to write first data to the host memory prior to the execution of any subsequent operations in the sequential order, and to execute the non-posted write operation so as to write second data to the host memory while allowing one or more of the subsequent operations in the sequential order to be executed prior to completion of writing the second data.Type: ApplicationFiled: July 26, 2017Publication date: January 31, 2019Inventors: Idan Burstein, Diego Crupnicoff
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Patent number: 10110518Abstract: A method for communication includes receiving at a receiving node over a network from a sending node a succession of data packets belonging to a sequence of transactions, including at least one or more first packets belonging to a first transaction and one or more second packets belonging to a second transaction executed by the sending node after the first transaction, wherein at least one of the second packets is received at the receiving node before at least one of the first packets. At the receiving node, upon receipt of the data packets, data are written from the data packets in the succession to respective locations in a buffer. Execution of the second transaction at the receiving node is delayed until all of the first packets have been received and the first transaction has been executed at the receiving node.Type: GrantFiled: December 18, 2013Date of Patent: October 23, 2018Assignee: Mellanox Technologies, Ltd.Inventors: Idan Burstein, Michael Kagan, Noam Bloch, Ariel Shachar, Hillel Chapman, Dror Bohrer, Diego Crupnicoff
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Patent number: 9996491Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.Type: GrantFiled: June 14, 2016Date of Patent: June 12, 2018Assignee: Mellanox Technologies, Ltd.Inventors: Diego Crupnicoff, Todd Wilde, Richard Graham, Michael Kagan
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Publication number: 20180004705Abstract: A method for data transfer includes transmitting a sequence of data packets, including at least a first packet and a second packet transmitted subsequently to the first packet, from a first computer over a network to a second computer in a single remote direct memory access (RDMA) data transfer transaction. Upon receipt of the second packet at the second computer without previously having received the first packet, a negative acknowledgment (NAK) packet is sent from the second computer over the network to the first computer, indicating that the first packet was not received. In response to the NAK packet, the first packet is retransmitted from the first computer to the second computer without retransmitting the second packet.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Adi Menachem, Ariel Shahar, Noam Bloch, Diego Crupnicoff, Michael Kagan
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Publication number: 20170255559Abstract: A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.Type: ApplicationFiled: March 2, 2016Publication date: September 7, 2017Inventors: Idan Burstein, Diego Crupnicoff, Shlomo Raikin, Michael Kagan
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Patent number: 9634940Abstract: A method includes receiving in a network switch of a communication network communication traffic that originates from a source node and arrives over a route through the communication network traversing one or more preceding network switches, for forwarding to a destination node. In response to detecting in the network switch a compromised ability to forward the communication traffic to the destination node, a notification is sent to the preceding network switches. The notification is to be consumed by the preceding network switches and requests the preceding network switches to modify the route so as not to traverse the network switch.Type: GrantFiled: March 19, 2015Date of Patent: April 25, 2017Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Zachy Haramaty, Eitan Zahavi, Freddy Gabbay, Diego Crupnicoff, Amiad Marelli, Gil Bloch
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Publication number: 20170093699Abstract: A method for congestion control includes receiving at a destination computer a packet transmitted on a given flow, in accordance with a predefined transport protocol, through a network by a transmitting network interface controller (NIC) of a source computer, and marked by an element in the network with a forward congestion notification. Upon receiving the marked packet in a receiving NIC of the destination computer, a congestion notification packet (CNP) indicating a flow to be throttled is immediately queued for transmission from the receiving NIC through the network to the source computer. Upon receiving the CNP in the transmitting NIC, transmission of further packets on at least the flow indicated by the CNP from the transmitting NIC to the network is immediately throttled, and an indication of the given flow is passed from the transmitting NIC to a protocol processing software stack running on the source computer.Type: ApplicationFiled: September 28, 2016Publication date: March 30, 2017Inventors: Diego Crupnicoff, Michael Kagan, Noam Bloch, Adi Menachem