Abstract: Systems and methods for synchronizing digital communications links, wherein one embodiment implemented in a receiver of a communications link comprises a shift register coupled to a transmission medium to receive synchronization data and a feedback circuit coupled to the shift register, wherein one or more cells of the shift register are configured to alternatively accept as input either a bit from a preceding cell or a received bit of synchronization data. The first occurs prior to synchronization, while the second occurs after synchronization. A counter is used to assert a signal indicating that the transmitter and receiver are synchronized.

Abstract: One embodiment of the present invention includes a system for communicating data comprising a device containing a flow-through buffer having a buffer capacity, a first data transport medium coupled to the device and a target coupled to the first data transport medium. The target device can be configured to, receive a data request from the device, send an initial set of data to the device that is smaller than the buffer capacity, delay a predetermined delay period, and send additional data to the device when the delay period has elapsed. By adjusting the amount of data sent in the initial data set and the delay period overfilling, and premature emptying of the flow-through buffer can be prevented or reduced.