Patents by Inventor Diego LORENZONI

Diego LORENZONI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12490376
    Abstract: A component carrier with an asymmetric build-up, which includes (a) a core; (b) a first stack at a first main surface of the core, the first stack having at least one first electrically conductive layer structure and a plurality of first electrically insulating layer structures; and (c) a second stack at a second main surface of the core, the second stack having at least one second electrically conductive layer structure and a plurality of second electrically insulating layer structures. At least two of the second electrically insulating layer structures are in direct contact with each other and each one of these electrically insulating layer structures has a smaller thickness than and/or includes a different material property than one of the first electrically insulating layer structures. Further described are methods for designing and manufacturing such an asymmetric component carrier.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: December 2, 2025
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Diego Lorenzoni, Mikael Andreas Tuominen, Seok Kim Tay
  • Publication number: 20250355062
    Abstract: A component carrier, including: i) a stack comprising at least two electrically conductive layer structures and at least one electrically insulating layer structure; ii) a plurality of components provided in or on the stack; iii) a plurality of electrically conductive interconnections in the stack electrically connecting at least one electrically conductive layer structure and a respective component; and iv) a test region provided in a portion of the component carrier, the test region comprising at least one test component and at least one second electrically conductive interconnection, the test component having the area where the second electrically conductive interconnection is connected with the same mechanical/chemical features and/or the same position in the depth of the correspondent one of the plurality of components, the second electrically conductive interconnection having the same mechanical/chemical features and/or the same position in the depth of at least one of the plurality of electrically cond
    Type: Application
    Filed: October 19, 2023
    Publication date: November 20, 2025
    Inventors: Diego LORENZONI, Linfeng LU, Jiajie DUANMU
  • Publication number: 20230217589
    Abstract: A component carrier with an asymmetric build-up, which includes (a) a core; (b) a first stack at a first main surface of the core, the first stack having at least one first electrically conductive layer structure and a plurality of first electrically insulating layer structures; and (c) a second stack at a second main surface of the core, the second stack having at least one second electrically conductive layer structure and a plurality of second electrically insulating layer structures. At least two of the second electrically insulating layer structures are in direct contact with each other and each one of these electrically insulating layer structures has a smaller thickness than and/or includes a different material property than one of the first electrically insulating layer structures. Further described are methods for designing and manufacturing such an asymmetric component carrier.
    Type: Application
    Filed: January 4, 2023
    Publication date: July 6, 2023
    Inventors: Diego LORENZONI, Mikael Andreas TUOMINEN, Seok Kim TAY