Patents by Inventor DIEM THY N. TRAN
DIEM THY N. TRAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11805645Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: August 16, 2019Date of Patent: October 31, 2023Assignee: Micron Technology, Inc.Inventors: Nicholas R. Tapias, Andrew Li, Adam W. Saxler, Kunal Shrotri, Erik R. Byers, Matthew J. King, Diem Thy N. Tran, Wei Yeeng Ng, Anish A. Khandekar
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Patent number: 11094697Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.Type: GrantFiled: November 7, 2018Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 11011523Abstract: Methods, apparatuses, and systems related to forming a capacitor column using a sacrificial material are described. An example method includes patterning a surface of a semiconductor substrate having: a first silicate material over the substrate, a first nitride material over the first silicate material, a sacrificial material over the first nitride material, a second silicate material over the sacrificial material, and a second nitride material over the second silicate material. The method further includes forming a column of capacitor material in an opening through the first silicate material, the first nitride material, the sacrificial material, the second silicate material, and the second nitride material. The method further includes removing the sacrificial material.Type: GrantFiled: January 28, 2019Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventors: Devesh Dadhich Shreeram, Diem Thy N. Tran, Sanjeev Sapra
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Patent number: 11004494Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.Type: GrantFiled: February 4, 2019Date of Patent: May 11, 2021Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
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Patent number: 10978553Abstract: Methods, apparatuses, and systems related to forming a capacitor using a hard mask material are described. An example method includes patterning a surface to have a first silicate material, a first nitride material on the first silicate material, a second silicate material on the first nitride material, a second nitride material on the second silicate material, and a sacrificial material on the second nitride material. The method further includes forming a hard mask material on the sacrificial material. The method further includes forming a capacitor material in an opening through the first silicate material, the first nitride material, the second silicate material, the second nitride material, the sacrificial material, and the hard mask material. The method further includes removing the sacrificial material and the hard mask material.Type: GrantFiled: January 28, 2019Date of Patent: April 13, 2021Assignee: Micron Technology, Inc.Inventors: Diem Thy N. Tran, Devesh Dadhich Shreeram, Sanjeev Sapra
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Publication number: 20210050364Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: August 16, 2019Publication date: February 18, 2021Applicant: Micro Technology, Inc.Inventors: Nicholas R. Tapias, Andrew Li, Adam W. Saxler, Kunal Shrotri, Erik R. Byers, Matthew J. King, Diem Thy N. Tran, Wei Yeeng Ng, Anish A. Khandekar
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Patent number: 10854611Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: GrantFiled: May 15, 2019Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 10847516Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: GrantFiled: July 2, 2019Date of Patent: November 24, 2020Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20200243536Abstract: Methods, apparatuses, and systems related to forming a capacitor column using a sacrificial material are described. An example method includes patterning a surface of a semiconductor substrate having: a first silicate material over the substrate, a first nitride material over the first silicate material, a sacrificial material over the first nitride material, a second silicate material over the sacrificial material, and a second nitride material over the second silicate material. The method further includes forming a column of capacitor material in an opening through the first silicate material, the first nitride material, the sacrificial material, the second silicate material, and the second nitride material. The method further includes removing the sacrificial material.Type: ApplicationFiled: January 28, 2019Publication date: July 30, 2020Inventors: Devesh Dadhich Shreeram, Diem Thy N. Tran, Sanjeev Sapra
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Publication number: 20200243640Abstract: Methods, apparatuses, and systems related to forming a capacitor using a hard mask material are described. An example method includes patterning a surface to have a first silicate material, a first nitride material on the first silicate material, a second silicate material on the first nitride material, a second nitride material on the second silicate material, and a sacrificial material on the second nitride material. The method further includes forming a hard mask material on the sacrificial material. The method further includes forming a capacitor material in an opening through the first silicate material, the first nitride material, the second silicate material, the second nitride material, the sacrificial material, and the hard mask material. The method further includes removing the sacrificial material and the hard mask material.Type: ApplicationFiled: January 28, 2019Publication date: July 30, 2020Inventors: Diem Thy N. Tran, Devesh Dadhich Shreeram, Sanjeev Sapra
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Patent number: 10553703Abstract: A method used in forming an array of elevationally-extending transistors comprises forming spaced lower conductive lines over a substrate. A gate insulator is formed in openings that are individually directly above individual of the lower conductive lines. The openings are formed into laterally-spaced lines comprising sacrificial material and are spaced longitudinally there-along. Channel material is formed in the individual openings laterally adjacent the gate insulator and is electrically coupled to the individual lower conductive line there-below. The sacrificial material is replaced with conductive-gate material. Other methods are disclosed including arrays of elevationally-extending transistors independent of method of manufacture.Type: GrantFiled: February 20, 2018Date of Patent: February 4, 2020Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20190326292Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20190267379Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: ApplicationFiled: May 15, 2019Publication date: August 29, 2019Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 10361204Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: GrantFiled: June 12, 2018Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Slmsek-Ege, Diem Thy N. Tran
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Patent number: 10319724Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: GrantFiled: July 12, 2018Date of Patent: June 11, 2019Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20190172517Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.Type: ApplicationFiled: February 4, 2019Publication date: June 6, 2019Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
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Patent number: 10242726Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.Type: GrantFiled: November 5, 2018Date of Patent: March 26, 2019Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
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Publication number: 20190088652Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.Type: ApplicationFiled: November 7, 2018Publication date: March 21, 2019Applicant: Micron Technology, Inc.Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 10163655Abstract: Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.Type: GrantFiled: November 20, 2015Date of Patent: December 25, 2018Assignee: Micron Technology, Inc.Inventors: Jin Lu, Rita J. Klein, Diem Thy N. Tran, Irina V. Vasilyeva, Zhiqiang Xie
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Patent number: 10157926Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.Type: GrantFiled: July 31, 2017Date of Patent: December 18, 2018Assignee: Micron Technology, Inc.Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran