Abstract: A processing unit (100) with a processor (110) for processing an operation code and a method for processing the operation code in the processing unit (100). The processor (110) comprises an operation code control unit (200) for receiving and processing the operation code in a boolean circuit (230) and generating a logical result thereof, and a next address control unit (210) comprising a multiplexing unit (250) with a plurality of input lines (A-D) selectable by the multiplexing unit (250) by means of the logical result of the boolean circuit (230). The processor (110) is triggerable by a trigger signal (CLOCK) and each operation code is processable by the processor (110) between successive trigger signals (CLOCK). When the trigger signal appears, the processor (110) issues a signal comprising an address of the operation code to be processed to the control memory (129) and/or a user data memory (140).

Abstract: A frequency and timing generator is presented with high accuracy and frequency resolution and no switching time between different timing cycles for a wide applicable frequency range, wherein the repetition rate of the timing cycles is not limited by the processing speed of the components. The frequency and timing generator according to the invention is accomplished by an apparatus for parallel processing of a series of timing signals comprising at least one processing unit for processing and calculating time values from timing parameters representing the series of timing signals, an output unit for outputting the series of timing signals, and an input unit for inputting the timing parameters. The sequences of n successive timing parameters to be parallelly processed are distributable by the input unit to n processing units.

Abstract: A technique for configuring improved circuit for generating an output sequence of values such as an output sequence used to test memory components or logic circuits. The inventive method is based on the fact that a factorially produced output sequence of values can be broken or divided into partial sequences and factors which may consist of either a single constant or a single mathematically definable term can be defined there from. The partial sequences may be combined by a multiplexor to form the output sequence. This permits a simple, inexpensive circuit for fast interleaving or pulse sequences to be designed. This can be accomplished by analyzing the desired output sequence of values to be created and arranging this output sequence in partial sequences determined by their periodicity.

Abstract: A method and apparatus for the computer-controlled generation of pulses which are arranged in intervals which intervals are grouped in a sequence that is to be repeated. The apparatus employs a preprocessor which supplies, to a revolver processor, data indicating the number and duration of immediately successive identical pulses in each of the intervals forming a sequence as well as data indicating the number of repetitions of the sequence. The first and the last pulse interval within the sequence to be repeated is marked. This data is cycled under clock control in the revolver processor which includes a data input station and a data output station. The clock-controlled cycled data reaching the output station is supplied, by a postprocessor, to a pulse cycle generator for generating the pulses.

Abstract: A circuit for generating product-specific digital test signals for testing memories, etc., the test signals comprising a test pulse occurring during a pulse interval and generated from predetermined data and timing signals. A format memory (7-11) stores addressable test signal formats (in the form of digital values denoting the test signals curve unrelated to time) for each data signal. These digital values are read out time parallel to each other and are combined by a flip-flop circuit (7-24) in the order of their occurrence during the pulse interval with timing signals for the respective data signal to form a control signal. The internal signal delay of the flip-flop circuit determining the generation of the test signals is invariably of the same value. This circuit may not only be used for test purposes but also generally for computer control, in particular for addressing main memories and buffers.

Abstract: The present invention is directed to a method of and and apparatus for continuously generating desired pulses during assumed successive desired pulse intervals with a very high time resolution by digitally predetermining the time values related to the start of the desired pulse intervals. These time values are divided into coarse and fine time rasters and coarse pulse intervals are generated from the assumed desired pulse intervals. The coarse pulses in the coarse time raster are generated from the desired pulses and each coarse pulse start and coarse pulse end, respectively is associated with a coarse pulse correction value. By adding the coarse pulse interval correction value to the coarse pulse correction value for the start and the end of the coarse pulse, respectively, a sum correction value is obtained and divided into a partial value associated with the fine time raster. The partial value of the sum correction value is used as a control value for a selected time delay for the coarse pulse edge shifted.

Abstract: In a method for the generation, without dead time, of pulses appearing in successive pulse intervals, with a high time resolution of the pulse intervals and of the pulses, the signals characterizing start (IIN1A, IIN2A) and end (IIN1E, IIN2E) of a pulse interval are generated under storage control by an oscillator (1) for giving coarse time raster values, and a delay circuit (3, 4) series-arranged with the oscillator (1) and with selective (7, 8) delay circuit taps (5, 6) for giving fine time raster values. The signals characterizing the pulse intervals are alternatingly applied to one of two paths (path I, path II), such that the signal characterizing the respective pulse interval start coincides with the coarse time raster predetermined by the oscillator (1). For each path, the leading and trailing edge of a pulse to be generated within a pulse interval is derived via oscillator clock-driven counters (45, 47, 46 and 48) loadable with a count, upon a specific count being reached.

Abstract: This discloses a pattern generator having a programmable product cycle timer in which a pulse train, i.e., the pattern generated, having a time raster measurable to one nanosecond can be repeated or switched from a first pulse frequency to a second pulse frequency without the usual transient switching periods between pulses. The invention accomplishes this by providing the generator with a cycle timer using a ten nanosecond clock operating in conjunction with a ten nanosecond down counter so that a pre-selected time interval, before the end of the pulse is achieved, a test is made to determine if a required condition needing a different pulse frequency exists. If such a condition does not exist the present pulse frequency is reinitiated so that at count 0 it is repeated without delay.