Abstract: This invention relates generally to the accessing of random access access memory arrays and, more specifically to circuits and techniques for increasing the data valid time of such memory arrays without increasing either the access or cycle times of the array. This is accomplished by providing, during a read cycle, a read signal directly to an output driver and simultaneously providing, via a parallel path, a latch output to the same driver. The latch output is provided under control of the read signal and a returning portion of a clock pulse such that the latch output overlaps the direct read signal from a read/write amplifier. An output is provided from the latch until it is reset and may last well into the next read cycle even when a new read signal is present.

Abstract: This invention relates generally to the static, random access, semiconductor memory arrays which incorporate split-emitter memory cells. The latter are accessed during a read cycle of a selected memory cell by precharging all the bit lines of unselected memory cells associated with the word line of the selected cell. This is accomplished by switchably connecting a voltage source to all the unselected bit lines which charges their bit line capacitances. Then, when read current sources are switchably connected to both the selected and unselected memory cells and the associated word line is switched to a WORD SELECT source, the read current associated with the unselected bit lines flows via charging switches to the precharge voltage sources and the read current associated with the selected bit lines along with dynamic current from uncharged selected bit line capacitances flows into the selected cell.