Abstract: The invention relates to a method, to a first and a second device (1, 2) and to a system (10) comprising the first and second device (1, 2) for transferring data, said system and devices matching the user data transfer rate during the data transfer between the first and the second device (1, 2). The first device (1) comprises in particular a medium access controller and operates in the second layer according to the OSI reference model, whilst the second device (2) transmits and receives user data in the first layer according to the OSI reference model and comprises an interface unit (24) for a DSL connection. The transfer rate match is achieved in particular by PAUSE frames according to the IEEE 802.3-2004 standard and the second device also operates in the second layer according to the OSI reference model to transmit and receive the PAUSE frames.

Abstract: A method for transmitting data is disclosed, whereby data are transmitted in packets between a first device and a second device, whereby a further device disposed between the first device and the second device analyzes the packets at most for regeneration purposes. The second device transmits data between itself and a third device using DSL technology. During the data transmission between the first device and the second device a comparison of transmission rates takes place.

Abstract: The invention relates to a method and a device for transmitting data, wherein when transmitting data with DSL technology transmission rates are compared.

Abstract: A method for transmitting data is disclosed, whereby data are transmitted in packets between a first device and a second device, whereby a further device disposed between the first device and the second device analyzes the packets at most for regeneration purposes. The second device transmits data between itself and a third device using DSL technology. During the data transmission between the first device and the second device a comparison of transmission rates takes place.

Abstract: A voltage generator circuit includes a storage capacitor with a terminal for pickup of an output voltage. A voltage generator device which can be turned on and off has an output being connected to the terminal of the storage capacitor. A first comparator device which can be turned on and off compares the output voltage with a first threshold voltage and generates a signal for turning the voltage generator device on and off. A second comparator device compares the output voltage with a second threshold voltage and generates an output signal with which the first comparator device is turned on and off.

Abstract: A charge pump assembly includes a storage capacitor having one terminal for a first supply potential and another terminal for pickup of an output potential. The assembly has one charge pump or two charge pumps being controlled by push-pull signals. Each charge pump includes a p-channel MOS transistor having a gate terminal being controlled by a first signal and having a drain-to-source path with one terminal being connected to the other terminal of the storage capacitor. A sliding capacitor has one terminal being connected to the other terminal of the drain-to-source path of the p-channel MOS transistor and another terminal being controlled by a second signal. An n-channel MOS transistor has a gate terminal being controlled by a third signal and a drain-to-source path being connected between a second supply potential and the one terminal of the sliding capacitor.

Abstract: A circuit array for amplifying and holding data with different supply voltages includes a first flip-flop being constructed in MOS technology for receiving a low supply voltage and data with a low supply voltage. The first flip-flop has output terminals. A second flip-flop being constructed in MOS technology receives a high supply voltage. The second flip-flop has a load segment and output terminals. At least one additional MOS transistor is connected in series with each of the output terminals of the second flip-flop between the load segment and ground. The at least one additional MOS transistor each has a gate terminal being connected to a respective one of the output terminals of the first flip-flip. A device for activating the first and second flip-flops is triggered for amplifying and holding the data to activate the first flip-flop and to activate the second flip-flop after a time delay.

Abstract: A regulating circuit for a substrate bias voltage generator for generating a substrate bias voltage in an integrated semiconductor circuit includes a Schmitt trigger circuit disposed between a first potential and a second potential of a semiconductor circuit. The Schmitt trigger circuit has an output side and an input for controlling a hysteresis function of the Schmitt trigger circuit. An inverter array is connected downstream of the output side of the Schmitt trigger circuit. The inverter array is connected to the first potential and to a first supply potential of the semiconductor circuit in terms of supply voltage, and the inverter array has an output. The input of the Schmitt trigger circuit for controlling the hysteresis function of the Schmitt trigger circuit is connected to the output of the inverter array.

Abstract: An integrated circuit for generating a reset signal includes terminals for a first and a second supply potential. A serial RC network is connected between the terminals. The RC network has an ohmic component, a capacitive component and a first circuit node of the integrated circuit connected between the components. An initializing circuit is connected parallel to the RC network. The initializing circuit has an output forming a second circuit node of the integrated circuit carrying a potential with a maximum value specified by dimensioning the initializing circuit, when the first supply potential is applied. An inverter circuit is connected between the first circuit node and the terminal for the second supply potential in terms of supply voltage. The inverter circuit has an input connected to the second circuit node and an output forming a third circuit node of the integrated circuit.