Abstract: An illustrative converter embodiment employs an oscillator comprising a capacitor and a comparator. The capacitor is alternately coupled to a charging current source and a discharging current source, the charging current source operating to charge the capacitor at a first rate and the discharging source operating to discharge the capacitor at a second rate. The comparator asserts an output signal when the capacitor charges to a first threshold voltage and deasserts the output signal when the capacitor discharges to a second threshold voltage. The first rate may be proportional to the input voltage and the second rate may be fixed. The output signal may be applied to the gate of a transistor to alternately apply the input voltage across an inductor and to apply current from the inductor to a capacitance. The duty cycle of the output signal is inversely proportional to the input voltage, or at least approximately so.

Abstract: Various disclosed leakage compensation apparatus and methods enable HV MOS transistors to be employed for ultralow current operation. One illustrative embodiment is a backup energy block that includes: a pair of input terminals that couple to a backup energy source; an anti-series switch that supplies power from the pair of input terminals to a voltage regulator (when closed) and isolates power from the pair of input terminals to the voltage regulator (when open); a control current source; and an HV MOS control transistor that selectively couples the control current source to a control signal line to open and close the anti-series switch; and a compensation current source coupled to the control signal line to provide a compensation current matched to a parasitic leakage current from the control transistor. The compensation current source includes an HV MOS compensation transistor matched to the control transistor.

Abstract: An illustrative converter embodiment employs an oscillator comprising a capacitor and a comparator. The capacitor is alternately coupled to a charging current source and a discharging current source, the charging current source operating to charge the capacitor at a first rate and the discharging source operating to discharge the capacitor at a second rate. The comparator asserts an output signal when the capacitor charges to a first threshold voltage and deasserts the output signal when the capacitor discharges to a second threshold voltage. The first rate may be proportional to the input voltage and the second rate may be fixed. The output signal may be applied to the gate of a transistor to alternately apply the input voltage across an inductor and to apply current from the inductor to a capacitance. The duty cycle of the output signal is inversely proportional to the input voltage, or at least approximately so.

Abstract: An illustrative converter embodiment employs an oscillator comprising a capacitor and a comparator. The capacitor is alternately coupled to a charging current source and a discharging current source, the charging current source operating to charge the capacitor at a first rate and the discharging source operating to discharge the capacitor at a second rate. The comparator asserts an output signal when the capacitor charges to a first threshold voltage and deasserts the output signal when the capacitor discharges to a second threshold voltage. The first rate may be proportional to the input voltage and the second rate may be fixed. The output signal may be applied to the gate of a transistor to alternately apply the input voltage across an inductor and to apply current from the inductor to a capacitance. The duty cycle of the output signal is inversely proportional to the input voltage, or at least approximately so.

Abstract: Various disclosed leakage compensation apparatus and methods enable HV MOS transistors to be employed for ultralow current operation. One illustrative embodiment is a backup energy block that includes: a pair of input terminals that couple to a backup energy source; an anti-series switch that supplies power from the pair of input terminals to a voltage regulator (when closed) and isolates power from the pair of input terminals to the voltage regulator (when open); a control current source; and an HV MOS control transistor that selectively couples the control current source to a control signal line to open and close the anti-series switch; and a compensation current source coupled to the control signal line to provide a compensation current matched to a parasitic leakage current from the control transistor. The compensation current source includes an HV MOS compensation transistor matched to the control transistor.

Abstract: An illustrative converter embodiment employs an oscillator comprising a capacitor and a comparator. The capacitor is alternately coupled to a charging current source and a discharging current source, the charging current source operating to charge the capacitor at a first rate and the discharging source operating to discharge the capacitor at a second rate. The comparator asserts an output signal when the capacitor charges to a first threshold voltage and deasserts the output signal when the capacitor discharges to a second threshold voltage. The first rate may be proportional to the input voltage and the second rate may be fixed. The output signal may be applied to the gate of a transistor to alternately apply the input voltage across an inductor and to apply current from the inductor to a capacitance. The duty cycle of the output signal is inversely proportional to the input voltage, or at least approximately so.

Abstract: A mixer is described having a Gilbert cell structure including a first input and a second input for inputting an RF signal, a third input and a fourth input for inputting a local oscillator signal, a first output and a second output for outputting an IF signal, a plurality of switches for converting the RF signal to an IF signal, and a dynamic bleed circuit for dynamically reducing the dc-current of the switches at the switching-point. As the dc-current of the switches is reduced at the point of commutation, the 1/f-noise is also strongly reduced without degrading the linearity. The switching happens at twice the local oscillator frequency. The mixer also includes a common mode feedback circuit that feeds the common mode signal, optionally amplified, to a common mode feedback control device that is in series between the dynamic bleed circuit and the supply voltage.

Abstract: An active RC filter has an op-amp and a biasing circuit arranged to bias the op-amp to set a gain bandwidth product of the op-amp according to a desired pole frequency of the filter. The biasing circuit is operable according to an output of an RC calibration circuit. The op-amp can be an OTA transconductance amplifier, and the biasing circuit can be arranged to maintain a constant product of R and transconductance at an input of the transconductance amplifier. This biasing can help to set the pole frequency more accurately and can thus reduce the need for bandwidth margin to be provided to allow for manufacturing process variations.

Abstract: A mixer is described having a Gilbert cell structure including a first input and a second input for inputting an RF signal, a third input and a fourth input for inputting a local oscillator signal, a first output and a second output for outputting an IF signal, a plurality of switches for converting the RF signal to an IF signal, and a dynamic bleed circuit for dynamically reducing the dc-current of the switches at the switching-point. As the dc-current of the switches is reduced at the point of commutation, the 1/f-noise is also strongly reduced without degrading the linearity. The switching happens at twice the local oscillator frequency. The mixer also includes a common mode feedback circuit that feeds the common mode signal, optionally amplified, to a common mode feedback control device that is in series between the dynamic bleed circuit and the supply voltage.

Abstract: An active RC filter has an op-amp and a biasing circuit arranged to bias the op-amp to set a gain bandwidth product of the op-amp according to a desired pole frequency of the filter. The biasing circuit is operable according to an output of an RC calibration circuit. The op-amp can be an OTA transconductance amplifier, and the biasing circuit can be arranged to maintain a constant product of R and transconductance at an input of the transconductance amplifier. This biasing can help to set the pole frequency more accurately and can thus reduce the need for bandwidth margin to be provided to allow for manufacturing process variations.

Abstract: A low noise differential amplifier has a pair of single ended common-gate or common-base circuits and cross coupling of an input of one of the pair to the gate or base of the other one of the pair. This cross-coupling puts the differential input voltage over the Gate-Source of the common-gate transistor (or Base-Emitter of the common base transistor). This means that the same input impedance and gain can be made with half the current compared to a basic common-gate topology. The cross-coupling means the noise generated by the positive side of the common-gate structure ends up partly on the negative output and vice versa, and so the Noise Figure can be less than 3 dB.

Abstract: A low noise differential amplifier has a pair of single ended common-gate or common-base circuits and cross coupling of an input of one of the pair to the gate or base of the other one of the pair. This cross-coupling puts the differential input voltage over the Gate-Source of the common-gate transistor (or Base-Emitter of the common base transistor). This means that the same input impedance and gain can be made with half the current compared to a basic common-gate topology. The cross-coupling means the noise generated by the positive side of the common-gate structure ends up partly on the negative output and vice versa, and so the Noise Figure can be less than 3 dB.