Abstract: In one embodiment, a device for communicating over a digital-subscriber-line (DSL) link comprises a digital-subscriber-line transceiver to transmit and receive data over the DSL link and a controller coupled to the digital-subscriber-line transceiver. The controller controls a non-intrusive adjustment of a transmitter that communicates over the DSL link.

Abstract: In one embodiment, a first device for communicating over a digital-subscriber-line (DSL) line comprises a digital-subscriber-line transceiver to transmit and receive data over the DSL link. A set of one or more performance parameters are associated with the DSL link by which the quality of the DSL link can be determined. The first device further comprises a controller coupled to the digital-subscriber-line transceiver. The controller causes a non-intrusive transmitter adjustment operation to be performed by the digital-subscriber-line transceiver.

Abstract: The present invention relates to a method and apparatus for testing components in ATM networks utilizing loop-back based ATM layer testing. The method and apparatus utilize interfaces and identifier codes to send and loop-back test cells along portions of virtual channels to test the virtual channels.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: The present invention relates to an apparatus and a method for providing failover operation of a communication link in a data communications network. In one embodiment the invention comprises a method for providing failover protection in a bidirectional data communication network, comprising the steps of: sending data from the first device to a second device, together with a first source identifier; detecting the source identifier of all data received by the first device; and, determining when either the source identifier of data received by the first device equals the source identifier of data sent by the first device or when the source identifier of data received by the first device does not equal a preset value, that a failure has occurred in a first communications link and in response to the failure deactivating the first communications link, and activating a second communications link.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing respective data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: A T1 digital PCM signal frame synchronizer includes a RAM memory for storing a complete extended superframe of received data, a pattern detector for detecting patterns in the memory that match a predetermined frame alignment signal, and a plurality of address pointer registers and associated counters. A given address within the RAM corresponds to a particular bit position within the received data. The first time that a pattern is detected at a given address within memory, that address is stored into a register, and its associated counter set to one. Subsequent pattern matches and violations at that address cause the counter to increment and decrement, respectively. A register whose counter value decrements down to zero becomes available for storing a new address. In-sync is declared when any counter exceeds an in-sync threshold. Out-of-sync is declared when that counter falls to an out-of-sync threshold or below.