Abstract: Data sequences comprised of figure-coded units, such as text comprised of ASCII characters, are encoded into another data entity, such as a pixel based image. The encoding implements a positionally-based encoding scheme in which values of the data entity (basic matrix) upon which the data sequences are to be encoded is used. The position for values to be changed in the basic matrix are determined by a reversible function, and the encoding value that these values are changed by may be 1, another arbitrary number, or determined by a formula. The counterpart to the reversible function is known by an intended receiver of the encoded data for decoding purposes. The basic matrix may be generated utilizing a suitably complex function, such as a chaos function, with parameters known only to the sender and receiver.

Abstract: Circuit arrangements (ULB) can be connected to one another with the assistance of a connection network (VN). Every circuit arrangement (ULB) can thereby operate as transmitter or as receiver. The connection network (VN) contains a matrix that is composed of a connection matrix and of an adjustment matrix. In the connection matrix, the data lines (DL) leading to the circuit arrangements (ULB) cross with coupling lines, whereby switching elements are arranged at the crossing locations. The adjustment matrix is composed of adjustment lines that cross with the coupling lines, whereby switching elements are arranged at the crossing locations. The connections between the data lines can be determined by programming the switching elements in the connection matrix and in the adjustment matrix and by applying an adjustment code to the adjustment matrix. The assistance of control signals can thereby be used to determine whether the data lines represent a data input or a data output.

Abstract: The logical operation of binary input signals can be carried out with a programmable circuit arrangement. It contains a matrix (MA) of crossing data lines (DL) and coupling lines (KL) at whose coupling locations switching elements (KE) are arranged corresponding to a function table to be realized. The switching elements (KE) can assume three statuses: one status corresponds to a binary 1 and the second status corresponds to a binary 0; the third status corresponds to a binary 1 or to a binary 0. Every data line (DL) can be operated as input or as output with the assistance of a control signal (ST) that is supplied to an input circuit and to an output circuit (AG). The input signals coupled from the data lines operated as input onto a coupling line (KL) are subjected to an AND operation on the coupling line. By contrast, the signals coupled from the coupling lines (KL) onto a data line (DL) wired as output are subjected to an OR operation on the data line.

Abstract: A programmable circuit for carrying out logic operations on binary input signals. The programmable circuit contains a matrix of first lines crossed with second lines thereby defining intersections at which logic units corresponding to a function table are connected. Two of the first lines are combined to form a line pair. The matrix is programmed in that a logic unit is connected between one of the lines of the line pair and a second line for the binary value of "1" and a logic unit is connected between the other of the lines of the line pair and the second line for programming a binary value of "0". Utilizing control signals, the logic units can be activated either in one direction or the other. Therefore, it is thus possible to set a line pair either as an input or as an output of the programmable circuit. When a line pair acts as an input, the binary signals coupled into the second lines by the logic units are subjected to an AND operation on the second lines.

Abstract: Given a programmable logic array, all product terms of the product matrix are applied to a prescribable potential by way of a first control signal so that the following sum matrix is no longer influenced by the input variables. Additional transfer elements are controllable by a second control signal, the additional transfer elements being assigned to additional terminal connecting points between the sum terms of the sum matrix. Depending upon the execution and employment of the logic array, the two control signals can be independent of one another, identical to one another, or inverted relative to one another.

Abstract: Error detection and correction apparatus for a programmable logic array (PLA) having AND and OR logic combinations merged therein is disclosed. The output lines from the AND and OR logic elements are coupled in such a manner that their functions form complete groups containing, if possible, all minterms. Missing minterms are added, as necessary, by special output lines or logic elements provided for that purpose to complete a group. If a minterm occurs on two or more function lines, the corresponding minterm is entered as a correction term into an error detection logic means, one of which is associated with each group of logic output lines. The error detection logic means are also utilized to test whether one, and only one, of the output lines in a grouping of function lines has a binary 1 value.Error correction signals are generated by mixed group error detection means, the inputs of which are connected to a function line of another function group.