Abstract: A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.

Abstract: A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.

Abstract: A first plurality of hardware description language (HDL) files defines a first scope of design forming only a subset of a larger hierarchical integrated circuit design. Technology-specific structures specific to a physical implementation are incorporated in the first scope of design. A second plurality of HDL files defining a first design entity that is at the first scope of design and that includes the technology-specific structures is generated. A third plurality of HDL files defining a second scope of design for the hierarchical integrated circuit design that is larger than and includes the first scope of design is formed. The third plurality of HDL files is processed to form a representation of the second scope of design. Processing the third plurality of HDL files includes replacing a second design entity in the second scope of design lacking at least some technology-specific structures with the first design entity.

Abstract: A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.

Abstract: A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.

Abstract: A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.

Abstract: A tool for machining materials has a main part and one or more blades. The main part is made of a low-alloy steel. The socket is welded to the main part, and the blade edges are made of a hard metal. The hard metal contains at least 82 vol. % of tungsten carbide and a metallic binder made of a cobalt-nickel-based alloy. The hardness of the hard metal is greater than 1350 HV10. The socket has a sintered composite, and 40 vol. % to 60 vol. % of the composite is composed of a metal carbide and a metallic binder. At least 95 vol. % of the metallic binder is made of nickel, and the hardness of the composite is less than 800 HV10.

Abstract: A tool for machining materials has a main part and one or more blades. The main part is made of a low-alloy steel. The socket is welded to the main part, and the blade edges are made of a hard metal. The hard metal contains at least 82 vol. % of tungsten carbide and a metallic binder made of a cobalt-nickel-based alloy. The hardness of the hard metal is greater than 1350 HV10. The socket has a sintered composite, and 40 vol. % to 60 vol. % of the composite is composed of a metal carbide and a metallic binder. At least 95 vol. % of the metallic binder is made of nickel, and the hardness of the composite is less than 800 HV10.

Abstract: The present invention relates to the identification of a TLR2 binding epitope wherein binding of a binding member to the epitope serves to inhibit TLR2 activation and/or signaling. Polypeptide fragments of TLR2 and three-dimensional structures comprising one or more amino acid residues His318, Pro320, Gln321 or Arg321, Tyr323, Lys347, Phe349, Leu371, Glu375, Tyr376 and His398 of TLR2 which define the identified epitope are provided for use in generating binding members. Also provided are binding members which bind to the identified epitope and methods of using same for the treatment and/or prevention of conditions associated with TLR2 activation and/or signaling.

Abstract: The present invention relates to the identification of a TLR2 binding epitope wherein binding of a binding member to the epitope serves to inhibit TLR2 activation and/or signalling. Polypeptide fragments of TLR2 and three-dimensional structures comprising one or more amino acid residues His318, Pro320, Gln321 or Arg321, Tyr323, Lys347, Phe349, Leu371, Glu375, Tyr376 and His398 of TLR2 which define the identified epitope are provided for use in generating binding members. Also provided are binding members which bind to the identified epitope and methods of using same for the treatment and/or prevention of conditions associated with TLR2 activation and/or signalling.

Abstract: The present invention relates to the identification of a TLR2 binding epitope wherein binding of a binding member to the epitope serves to inhibit TLR2 activation and/or signalling. Polypeptide fragments of TLR2 and three-dimensional structures comprising one or more amino acid residues His318, Pro320, Gln321 or Arg321, Tyr323, Lys347, Phe349, Leu371, Glu375, Tyr376 and His398 of TLR2 which define the identified epitope are provided for use in generating binding members. Also provided are binding members which bind to the identified epitope and methods of using same for the treatment and/or prevention of conditions associated with TLR2 activation and/or signalling.

Abstract: An aspect includes a computer program product for implementing a model of an electrical circuit including a first region and a second region, the first region including simulated logic and a simulated latch circuit. The computer program product includes a tangible storage medium readable by a processing circuit for performing a method. The method includes receiving, as simulated logical inputs to the simulated logic a simulated power supply voltage state of the first region, a simulated data input signal and a simulated clock signal. The method also includes generating, based on determining that the simulated power supply voltage state of the first region corresponds to an inactive state of the first region, a pseudo-random number as an output of the simulated latch circuit, the pseudo-random number generated based on the simulated data input signal and the simulated data output signal from the simulated latch circuit.

Abstract: The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model (22) is compiled for integrating a plurality of n different instantiations (12A, . . . 12N) of the same hardware model, and facilities and signals of different instantiations are resolved by instantiation-specific name space specifications in a code switch (24,26). Thus, computing time is saved because by simulating the meta model, the processor resources, for instance, storage spaces, are utilized more efficiently.

Abstract: The present invention relates to the processing of hardware simulator instruction requests. A request broker is processing high-level simulator instruction requests submitted by different drivers. A high-level instruction request comprises multiple simulator instructions. The request broker is receiving and splitting the requests into simulator instructions. The instructions are put in a request queue associated to the driver originating the request. The request broker is then processing the request queues in a round-robin fashion and submits the instructions in a queue to the simulator until a clock instruction needs to be submitted. Then the next queue is processed. When only clock instructions need to be submitted, the minimum number of clock cycles is determined and submitted in a new instruction to the simulator. This minimum number is then subtracted from the clock instructions in the queues, and the drivers are queried for new requests.

Abstract: The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model (22) is compiled for integrating a plurality of n different instantiations (12A, . . . 12N) of the same hardware model, and facilities and signals of different instantiations are resolved by instantiation-specific name space specifications in a code switch (24,26). Thus, computing time is saved because by simulating the meta model, the processor resources, for instance, storage spaces, are utilized more efficiently.

Abstract: Phenylamidines of the formula (I) wherein: R6 is a C5-12-alkyloxycarbonyl group, and R7 is a hydrogen atom, or a C1-8-alkyl, C4-7-cycloalkyl, phenyl-C1-4-alkyl, or R8—CO—OCHR9— group, wherein R8 is a C1-4-alkyl, C1-4-alkoxy, C3-7-cycloalkyl, or C4-7-cycloalkoxy group, and R9 is a hydrogen atom or a C1-4-alkyl group, or a tautomer or pharmaceutically acceptable salt thereof. These compounds inhibit cell aggregation and are useful for the treatment or prevention of thrombosis, inflammation, bone degradation, tumors and tumor metastasis.

Abstract: Disclosed is a hardware design development tool, where in a first step the data flow (30) of the desired hardware design is specified (10, 40) and structured into functions. Then the required control logic (31, 32) is introduced in those functions in order to get a description of the functional behavior of the underlying hardware. Various interconnections or relationships are provided between data flow and control logic, for instance via calls (33) between them. According to the proposed methodological steps, the design is specified (10, 40) by functions depending on variables, wherein the functions contain data flow and control flow information. The functional description is parsed (43) in order to distinguish data flow and control flow information. In particular, at least one local table (45) each entry of which containing the control flow information, and a global table (46) each entry of which containing the data flow information and references to the local table(s), are provided.

Abstract: The invention relates to new labelled fibrinogen receptor antagonists which have an affinity for the receptor which is comparable to or greater than that of .sup.125 I-fibrinogen and whose binding is not disrupted by foreign proteins.

Abstract: The invention relates to a process for treating cast iron melts with silicon carbide. In this process, the silicon carbide used is subjected, before being introduced into the cast iron melt, to an oxidizing treatment in such a manner that the individual SiC granules are coated with a covering containing silica. A silicon carbide of this quality can be manufactured, for example, by subjecting the SiC in granular form, in a static or agitated mass, to an oxidizing atmosphere, such as air, oxygen or water vapor, at temperatures within the range of 900.degree.-1600.degree. C. and subsequently subjecting the agglomerates formed to gentle comminution to expose the SiC surfaces which, as a result of the formation of an agglomerate, completely or partially escaped the oxidizing attack.

Abstract: In a conveyor for feeding non-slidable goods into a continuously operating packing machine, and wherein spacing between the goods being conveyed is provided by elongated engaging bars spaced from each other, a storage device is provided at the inlet portion of the conveyor. The engaging bars are discharged from the storage device onto the conveyor band of the conveyor at predetermined intervals controlled by a programming shaft of the packing machine. The engaging bars have flexible, deformable elements which are clamped between the conveyor band and clamping driven endless belts so that the engaging bars are retained on the conveyor band at predetermined intervals from each other.