Patents by Inventor Dieter W. Spaderna

Dieter W. Spaderna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of operating data buffer apparatus
    Patent number: 4875196
    Abstract: An improved First-In, First-Out data buffer and method of operation incorporates a plurality of arrays of random-access memory cells in column and row orientation per array in which all the cells in a row of one array are precharged simultaneously as memory cells are accessed for read or write operations in another array. Also, all the cells in a row of the other array may be precharged as the memory cells in the one array are accessed independently for read or write operations. Accesses to memory cells in addressed rows alternate from one array to another so that the signal conditioning of the memory cells in one array can take place before access in needed and while memory cells are being accessed in another array. Improved status logic unambigously designates the conditions of empty, half full and full, independent of the sequence of data read and write operations.
    Type: Grant
    Filed: September 8, 1987
    Date of Patent: October 17, 1989
    Assignee: Sharp Microelectronic Technology, Inc.
    Inventors: Dieter W. Spaderna, Jeffrey L. Miller
  • Multiple bit dynamic random-access memory
    Patent number: 4547867
    Abstract: A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.
    Type: Grant
    Filed: April 11, 1983
    Date of Patent: October 15, 1985
    Assignee: Intel Corporation
    Inventors: Edmund A. Reese, Dieter W. Spaderna, Stephen T. Flannagan
  • Multiple bit output dynamic random-access memory
    Patent number: 4453237
    Abstract: A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.
    Type: Grant
    Filed: April 11, 1983
    Date of Patent: June 5, 1984
    Assignee: Intel Corporation
    Inventors: Edmund A. Reese, Dieter W. Spaderna, Stephen T. Flannagan
  • Multiple bit output dynamic random-access memory
    Patent number: 4406013
    Abstract: A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.
    Type: Grant
    Filed: October 1, 1980
    Date of Patent: September 20, 1983
    Assignee: Intel Corporation
    Inventors: Edmund A. Reese, Dieter W. Spaderna, Stephen T. Flannagan