Abstract: An exhaust gas after-treatment device includes: a catalytic converter system, which includes a delivery side and a discharge side; and a container including an interior space and at least two openings, the at least two openings including a first opening and a second opening, the catalytic converter system being arranged in the interior space of the container, the first opening being connected with the catalytic converter system on the delivery side, and the second opening being connected to the catalytic converter system on the discharge side.

Abstract: A signal processor includes at least one data source (3), a plurality of input registers (11, 12, 13, 14, . . . ) whose inputs are coupled to the data source by data buses (9, 10), a plurality of multipliers (19, 20; 71, 72 . . . ) for multiplying data buffered in the input registers, and a processing arrangement spread over a plurality of data processor branches (4-0, 4-1, . . . , 4-N) for processing products (p0, p1, . . . ), generated by the multipliers by arithmetic and/or logic operations. For achieving enhanced flexibility of the signal processor and increasing the number of possible applications, multiplexers (15, 16, 17, 18; 70) are provided which are used for coupling the multipliers to a respective part of the input registers in dependence on control signals (I, II, III, IV). Such a signal processor is preferably used in mobile radio technology. Further fields of application are, for example, audio, video, medical and automotive technology, ISDN systems, and digital radio.

Abstract: A signal processor is disclosed having a program memory which stores compressed program instructions and a decoder device which decodes the compressed program instructions to form decoded program instructions for controlling functions of the signal processor. The decoder device has a programmable decoder and a fixed decoding arrangement, where the fixed decoding arrangement is non-programmable and hardwired for decoding the compressed program instructions using logical operations. The programmable decoder includes a decoder memory, such as a ROM or RAM, having cells for storing the decoded program instructions in an uncompressed form. These cells are addressed for executing programmable decoding functions of the programmable decoder. The compressed program instructions include a first number of bits for determining a category of the compressed program instructions and a second number of bits for determining the address of the cells.

Abstract: Complex coding of speech signals, as this is used, for example, in the GSM half rate speech coder, requires the use of a signal processor. On the other hand, a hands-free facility requires an arithmetic unit which adaptively calculates filter coefficients. This is only effected during speech pauses in which the speech coder is switched to a mode in which it generates codes for background noise with only little processing circuitry and expense. According to the invention, the signal processor for the coding device is therefore used for calculating the coefficients for the echo cancelling filter during speech pauses. This requires the use of not more than a single signal processor which can thus be used twice.

Abstract: A signal processor which includes a first data processing unit for processing data supplied thereto by a data bus system which operates in successive command cycles, and at least one further data processing unit operating in parallel with the first processing unit to process data supplied from the first processing unit during the command cycles. Since the further processing unit does not receive data from the bus system, that processor and still further processors can be added without requiring extension of the bus system. The parallel operation of a plurality of processing units achieves enhanced speed of computation, so that the signal processor is particularly adapted to computation of auto-correlation and cross-correlation functions and for FIR digital filtering.

Abstract: When speech data are transmitted via radio in the European mobile radio telephone system according to the GSM standard, always 20 ms speech data are transmitted as source-coded code words between the mobile stations and the fixed stations. The fixed stations are again connected to a central station via a connection having a smaller bandwidth, in which central station the speech decoders are arranged. Since transmission errors which cannot be corrected by the channel decoder in prior-art system are masked in the channel decoder in the central station, only a very simple error masking option is provided. According to the invention, the channel decoder which is arranged in the mobile and fixed stations close to the receiver, more signals are derived which feature the reliability of the received data and, in dependence on these additional data, extensive different error masking measures are carried out on the received code words. This does not only take place in the mobile station, but also in the fixed station.

Abstract: In so-called Code Excited Linear Prediction (CELP) coding methods for speech signal transmission, a codebook look-up method is used which is very processor-intensive. To conserve power, during speech pauses not only the transmitter but also the speech coder is turned off substantially completely. Consequently, when the speech signal resumes there is a transition interval before the filters of the speech coder become adjusted to full operation. For this reason, according to the invention, the filters are not turned off during speech pauses but are directly driven by codebook excitation vectors which correspond to the speech signal then being processed. As a result, there is a smoother and hardly perceptible transition between background noise and the speech signal when the latter resumes. An artificial background noise is produced in the receiver during speech pauses.

Abstract: Digital signal processing often requires the fast summing of a chain of products. Known signal processors often use two separate dam buses via which the values to be multiplied are supplied in parallel, it being assumed that these values originate from different sources, for example from different memories. Because a product of two binary numbers has double the number of positions, therefore, an adder having double the word width is also used. In order to reduce this substantial expenditure at the expense of only a slight reduction in speed, an adder is provided having only the single word width and to process the most-significant and least-significant bits of the product during two successive clock periods. The values to be multiplied can then be supplied successively.