Patents by Inventor Dietmar Orendi

Dietmar Orendi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • On-chip test technique for low drop-out regulators
    Patent number: 9465086
    Abstract: A circuit and method is described for automatically testing multiple LDO regulator circuits on an integrated circuit chip independent of an ATE. Each LDO regulator is tested for voltage at a specified current output capability, wherein the output driver transistor is formed by at least two pass transistors, which are each tested for voltage output at a particular current capability. The test results are delivered back to the ATE and for a failed test, the gate voltage of the pass device can be observed through an analog multiplexer to enable debug.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: October 11, 2016
    Assignee: Dialog Semiconductor GmbH
    Inventors: Dietmar Orendi, Biren Minhas, Robert Baraniecki
  • Novel On-Chip Test Technique for Low Drop-Out Regulators
    Publication number: 20150377981
    Abstract: A circuit and method is described for automatically testing multiple LDO regulator circuits on an integrated circuit chip independent of an ATE. Each LDO regulator is tested for voltage at a specified current output capability, wherein the output driver transistor is formed by at least two pass transistors, which are each tested for voltage output at a particular current capability. The test results are delivered back to the ATE and for a failed test, the gate voltage of the pass device can be observed through an analog multiplexer to enable debug.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Dietmar Orendi, Biren Minhas, Robert Baraniecki
  • On-chip test technique for low drop-out regulators
    Patent number: 9151804
    Abstract: A circuit and method is described for automatically testing multiple LDO regulator circuits on an integrated circuit chip independent of an ATE. Each LDO regulator is tested for voltage at a specified current output capability, wherein the output driver transistor is formed by at least two pass transistors, which are each tested for voltage output at a particular current capability. The test results are delivered back to the ATE and for a failed test, the gate voltage of the pass device can be observed through an analog multiplexer to enable debug.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: October 6, 2015
    Assignee: Dialog Semiconductor GmbH
    Inventors: Dietmar Orendi, Biren Minhas, Robert Baraniecki
  • On-Chip Test Technique for Low Drop-Out Regulators
    Publication number: 20130265060
    Abstract: A circuit and method is described for automatically testing multiple LDO regulator circuits on an integrated circuit chip independent of an ATE. Each LDO regulator is tested for voltage at a specified current output capability, wherein the output driver transistor is formed by at least two pass transistors, which are each tested for voltage output at a particular current capability. The test results are delivered back to the ATE and for a failed test, the gate voltage of the pass device can be observed through an analog multiplexer to enable debug.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 10, 2013
    Applicant: DIALOG SEMICONDUCTOR GMBH
    Inventors: Dietmar Orendi, Biren Minhas, Robert Baraniecki