Patents by Inventor Dietmar Schmunkamp
Dietmar Schmunkamp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10169233Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.Type: GrantFiled: June 5, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
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Patent number: 10169234Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.Type: GrantFiled: October 23, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
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Publication number: 20180349277Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.Type: ApplicationFiled: June 5, 2017Publication date: December 6, 2018Inventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
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Publication number: 20180349278Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.Type: ApplicationFiled: October 23, 2017Publication date: December 6, 2018Inventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
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Patent number: 8868975Abstract: A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.Type: GrantFiled: August 2, 2011Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Ralph E. Bellofatto, Steven M. Douskey, Rudolf A. Haring, Moyra K. McManus, Martin Ohmacht, Dietmar Schmunkamp, Krishnan Sugavanam, Bryan J. Weatherford
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Publication number: 20130031418Abstract: A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.Type: ApplicationFiled: August 2, 2011Publication date: January 31, 2013Applicant: International Business Machines CorporationInventors: Ralph E. Bellofatto, Steven M. Douskey, Rudolf A. Haring, Moyra K. McManus, Martin Ohmacht, Dietmar Schmunkamp, Krishnan Sugavanam, Bryan J. Weatherford
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Patent number: 7996715Abstract: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.Type: GrantFiled: November 5, 2008Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Karin Rebmann, Dietmar Schmunkamp, Tobias Webel, Thomas E. Gilbert, Timothy G. McNamara, Patrick J. Meaney
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Patent number: 7966536Abstract: A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.Type: GrantFiled: April 11, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: Ralf Ludewig, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Tobias Webel
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Publication number: 20090259899Abstract: A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.Type: ApplicationFiled: April 11, 2008Publication date: October 15, 2009Inventors: Ralf Ludewig, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Tobias Webel
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Patent number: 7568138Abstract: A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation for a functional unit, protection logic allows a scan enable to activate to the functional unit only if the logic clocks are stopped to that functional unit, otherwise the scan enable is not activated, an error is indicated, and an interrupt is presented to firmware. Also, in response to a command from a firmware interface to stop the logic clocks to a functional unit, protection logic allows the clocks to be stopped to the functional unit only if the functional unit is already indicating a catastrophic error, otherwise the clocks are not stopped, an error is indicated, and an interrupt is presented to firmware.Type: GrantFiled: July 26, 2006Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Adolf Martens, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Ching-Lung L. Tong, Tobias Webel
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Publication number: 20090070622Abstract: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.Type: ApplicationFiled: November 5, 2008Publication date: March 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karin Rebmann, Dietmar Schmunkamp, Tobias Webel, Thomas E. Gilbert, Timothy G. McNamara, Patrick J. Meaney
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Patent number: 7484118Abstract: The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.Type: GrantFiled: December 16, 2004Date of Patent: January 27, 2009Assignee: International Business Machines CorporationInventors: Karin Rebmann, Dietmar Schmunkamp, Tobias Webel, Thomas E. Gilbert, Timothy G. McNamara, Patrick J. Meaney
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Publication number: 20080028266Abstract: A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation for a functional unit, protection logic allows a scan enable to activate to the functional unit only if the logic clocks are stopped to that functional unit, otherwise the scan enable is not activated, an error is indicated, and an interrupt is presented to firmware. Also, in response to a command from a firmware interface to stop the logic clocks to a functional unit, protection logic allows the clocks to be stopped to the functional unit only if the functional unit is already indicating a catastrophic error, otherwise the clocks are not stopped, an error is indicated, and an interrupt is presented to firmware.Type: ApplicationFiled: July 26, 2006Publication date: January 31, 2008Inventors: Adolf Martens, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Ching-Lung L. Tong, Tobias Webel
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Patent number: 7308592Abstract: The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.Type: GrantFiled: February 11, 2005Date of Patent: December 11, 2007Assignee: International Business Machines CorporationInventors: Dietmar Schmunkamp, Andreas Wagner, Tobias Webel, Ulrich Weiss
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Publication number: 20060184814Abstract: The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Inventors: Dietmar Schmunkamp, Andreas Wagner, Tobias Webel, Ulrich Weiss
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Publication number: 20050149802Abstract: The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.Type: ApplicationFiled: December 16, 2004Publication date: July 7, 2005Applicant: International Business Machines CorporationInventors: Karin Rebmann, Dietmar Schmunkamp, Tobias Webel, Thomas Gilbert, Timothy McNamara, Patrick Meaney
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Patent number: 5964845Abstract: One or more processing units are connected with a clock component (comprising a clock) over a bi-directional serial link, and data frames are transmitted between the clock component and the processing units. The clock component may contain a serial link combination circuit for combining multiple processing unit serial links, operating in parallel, into a single serial link connected to the clock. Both of the clock component and the processing units contain an error detection and correction mechanism which examine and modify data within the data frames to perform error detection and correction. The clock component optionally contains an external interface for connection to a command-issuing Service Processor.Type: GrantFiled: December 16, 1996Date of Patent: October 12, 1999Assignee: International Business Machines CorporationInventors: Robert Braun, Wilhelm Haller, Klaus Jorg Getzlaff, Thomas Pfluger, Dietmar Schmunkamp
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Patent number: 5956563Abstract: The invention relates to a method for reducing a transient thermal mismatch between a first component and a second component which are in mechanical contact with one another. The temperature of the first component is controlled by the amount of energy dissipated thereby. The amount of energy dissipated is controlled as a function of a data pattern input into the first component which causes a certain number of gates within the component to switch per clock cycle. By determining the desired energy dissipation in terms of the number of gates which are to be switched and arranging the input data pattern accordingly, the thermal mismatch between the components may be reduced.Type: GrantFiled: January 9, 1997Date of Patent: September 21, 1999Assignee: International Business Machines CorporationInventors: Erich Klink, Dietmar Schmunkamp, Helmut Weber, Roland Frech, Bernd Garben, Hubert Harrer
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Patent number: 5306959Abstract: An electrical circuit for generating clock pulses for a multi-chip computer system which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clock splitter circuit is provided on the clock generation circuit. This clock splitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clock splitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clock splitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.Type: GrantFiled: March 26, 1992Date of Patent: April 26, 1994Assignee: International Business Machines CorporationInventors: Guenter Knauft, Bernd Leppla, Dietmar Schmunkamp, Ulrich Weiss
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Patent number: 4896323Abstract: A clock generator system is provided which includes several clock generators each containing a feedback shift register. A parity bit is calculated over the output of all shift registers and compared to an expected value. Additionally, a parity bit is calculated for each shift register, over the bits stored in the shift register, the number of ONE bits in a shift register being constant. A parity error at the output of the shift registers in combination with an error in the additional parity bit allows the correction of the erroneous clock pulse generated by the shift register in error.Type: GrantFiled: June 6, 1988Date of Patent: January 23, 1990Assignee: International Business Machines Corp.Inventors: Stefan Korner, Klaus D. Muller, Peter Rudolph, Dietmar Schmunkamp, Halim S. Tandjung