Abstract: In a device, a pulse modulation switching logic is provided to generate switching signals of a pulse modulator so as to generate a pulse modulated signal with a first pulse modulation control parameter and a second pulse modulation control parameter. The first pulse modulation control parameter is controlled on the basis of a first control signal, and the second pulse modulation control parameter is controlled on the basis of a second control signal. A first control loop is provided to generate the first control signal from an output signal derived from the pulse modulated signal. A second control loop is provided to generate the second control signal on the basis of the output signal. The first and second control signals are applied to concurrently control the first and second pulse modulation control parameters.

Abstract: An analog-to-digital converter arrangement may include an analog amplifier with variable gain; an analog-to-digital converter; a digital reconstruction element including elements to reduce an influence of transients during a change of the variable gain of the analog amplifier.

Abstract: In a device, a pulse modulation switching logic is provided to generate switching signals of a pulse modulator so as to generate a pulse modulated signal with a first pulse modulation control parameter and a second pulse modulation control parameter. The first pulse modulation control parameter is controlled on the basis of a first control signal, and the second pulse modulation control parameter is controlled on the basis of a second control signal. A first control loop is provided to generate the first control signal from an output signal derived from the pulse modulated signal. A second control loop is provided to generate the second control signal on the basis of the output signal. The first and second control signals are applied to concurrently control the first and second pulse modulation control parameters.

Abstract: Implementations related to echo cancellation are depicted and described herein.

Abstract: This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching.

Abstract: The invention creates a method for adapting filter cut-off frequencies for the transmission of discrete multitone symbols, where a transmit symbol datastream consisting of discrete multitone symbols is applied to an interpolation device, the transmit symbol datastream is interpolated with a symbol rate in the interpolation device, an interpolated symbol datastream is filtered in a first low-pass filtering device in accordance with a first filter cut-off frequency, which can be predetermined by a first filter cut-off frequency determining device, a digital symbol datastream obtained after a digital-analog conversion, transmission and analog-digital conversion, is filtered at the receiver end in a second low-pass filtering device in accordance with a second filter cut-off frequency, which can be predetermined by a second filter cut-off frequency determining device, in order to provide an equalized symbol datastream, the equalized symbol datastream is decimated in a decimation device and the decimated received s

Abstract: In a device, a pulse modulation switching logic is provided to generate switching signals of a pulse modulator so as to generate a pulse modulated signal with a first pulse modulation control parameter and a second pulse modulation control parameter. The first pulse modulation control parameter is controlled on the basis of a first control signal, and the second pulse modulation control parameter is controlled on the basis of a second control signal. A first control loop is provided to generate the first control signal from an output signal derived from the pulse modulated signal. A second control loop is provided to generate the second control signal on the basis of the output signal. The first and second control signals are applied to concurrently control the first and second pulse modulation control parameters.

Abstract: A method for adapting filter cut-off frequencies for the transmission of discrete multitone symbols, where a transmit symbol datastream consisting of discrete multitone symbols is applied to an interpolation device, the transmit symbol datastream is interpolated with a symbol rate in the interpolation device, an interpolated symbol datastream is filtered in a first low-pass filtering device in accordance with a first filter cut-off frequency, which can be predetermined by a first filter cut-off frequency determining device, a digital symbol datastream obtained after a digital-analog conversion, transmission and analog-digital conversion, is filtered at the receiver end in a second low-pass filtering device in accordance with a second filter cut-off frequency, which can be predetermined by a second filter cut-off frequency determining device, in order to provide an equalized symbol datastream, the equalized symbol datastream is decimated in a decimation device and the decimated received symbol datastream consi

Abstract: A nonlinear converter, such as a DC-DC converter, includes a nonlinear controller configured to receive an output voltage and a current, and configured to generate a PWM signal. The PWM signal is generated based on setting the converter to a first phase associated with both buck and boost modes when a clock signal is asserted, and selecting a second phase associated with the buck mode of the converter, if a sliding function signal achieves a first predetermined relationship with respect to a buck threshold before a next clock signal is asserted, or selecting a third phase associated with the boost mode of the converter, if the sliding function signal achieves a second predetermined relationship with respect to a boost threshold before a next clock signal is asserted. The nonlinear converter may include a power stage configured to provide the output voltage and a coil current to the nonlinear controller.

Abstract: Disclosed herein are devices, methods, and techniques including analog to digital converters having at least one digital filter.

Abstract: Disclosed herein are devices, methods, and techniques including analog to digital converters having at least one digital filter.

Abstract: Techniques for reducing quantization error in electronic components are described herein.

Abstract: Techniques for reducing sampling error in electronic components are described herein.

Abstract: This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching.

Abstract: Implementations and embodiments of decoders, encoder/decoder systems and converters are depicted and described.

Abstract: The method is used for limiting the power of a transmission-end signal (xn) compiled from a plurality of differently spread-coded signals. In this context, it is assumed that the quantity of spread codes used for the differently spread-coded signals is known as code engagement information (Cch,SF,k; 80). First, correction spread codes are selected by virtue of the engagement information (Cch,SF,k; 80) being evaluated. On the basis of the selected correction codes, a spread-coded correction signal (y?n) is formed which is overlaid with the compiled signal (xn).

Abstract: A multiple output time-to-digital converter (TDC) and an Analog-to-Digital Converter (ADC) incorporating the multiple output TDC is disclosed.

Abstract: A multiple output time-to-digital converter (TDC) and an Analog-to-Digital Converter (ADC) incorporating the multiple output TDC is dislosed.

Abstract: A method and a device for interpolating or decimating a signal is provided, the signal being processed by a plurality of signal processing means connected in series, which at least comprise means for increasing or reducing a clock rate of the signal and filtering means. To achieve adaptation to different operating modes or transmission standards, individual portions of the signal processing means connected in series can be bridged by bypasses. In addition, filtering parameters of the filtering means can be varied and factors, by which a clock rate of the signal is increased or reduced, can be changed.

Abstract: Implementations related to echo cancellation are depicted and described herein.