Abstract: In accordance with an embodiment, a circuit includes an oscillator having an oscillation frequency dependent on an input signal, a digital accumulator having a first input coupled to an output of the oscillator, a digital-to-analog converter (DAC) coupled to an output of the digital accumulator, an analog loop filter coupled to an output of the digital-to-analog converter, and a comparison circuit having an input coupled to an output of the analog loop filter and an output coupled to a second input of the digital accumulator.

Abstract: Disclosed are techniques for reducing noise and providing conversion signals in electronic components, including pulse width modulation (PWM) oversampling converters, by performing signal conversion having finite impulse response (FIR) feedback. Implementations may reduce the sensitivity of the conversion process to jitter in the sampling clock, thereby reducing noise and providing conversion signals.

Abstract: The method is used for limiting the power of a transmission-end signal (xn) compiled from a plurality of differently spread-coded signals. In this context, it is assumed that the quantity of spread codes used for the differently spread-coded signals is known as code engagement information (Cch,SF,k; 80). First, correction spread codes are selected by virtue of the engagement information (Cch,SF,k; 80) being evaluated. On the basis of the selected correction codes, a spread-coded correction signal (y?n) is formed which is overlaid with the compiled signal (xn).

Abstract: Disclosed are techniques for reducing noise and providing conversion signals in electronic components, including pulse width modulation (PWM) oversampling converters, by performing signal conversion having finite impulse response (FIR) feedback. Implementations may reduce the sensitivity of the conversion process to jitter in the sampling clock, thereby reducing noise and providing conversion signals.

Abstract: Techniques for reducing quantization error in electronic components are described herein.

Abstract: Techniques for converting signals using finite impulse response (FIR) feedback are described herein.

Abstract: A method and a device for interpolating or decimating a signal is provided, the signal being processed by a plurality of signal processing means connected in series, which at least comprise means for increasing or reducing a clock rate of the signal and filtering means. To achieve adaptation to different operating modes or transmission standards, individual portions of the signal processing means connected in series can be bridged by bypasses. In addition, filtering parameters of the filtering means can be varied and factors, by which a clock rate of the signal is increased or reduced, can be changed.

Abstract: Techniques for converting signals using finite impulse response (FIR) feedback are described herein.

Abstract: Techniques for reducing sampling error in electronic components are described herein.

Abstract: This disclosure relates to adjusting a limit cycle frequency of a pulse width modulation in an analog to digital converter as a function of an input signal level to increase dynamic range.

Abstract: Techniques for reducing quantization error in electronic components are described herein.

Abstract: This disclosure relates to adjusting a limit cycle frequency of a pulse width modulation in an analog to digital converter as a function of an input signal level to increase dynamic range.

Abstract: Techniques for reducing sampling error in electronic components are described herein.

Abstract: Techniques for reducing sampling error in electronic components are described herein.

Abstract: Techniques for reducing quantization error in electronic components are described herein.

Abstract: Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).

Abstract: The invention provides a method for transmitting an analog data stream (101) from a data stream transmitter (214) to a data stream receiver (215) by means of discrete multitone symbols (208), in which data (123) to be transmitted are input into a data input device (201) of the data stream transmitter (214), the data to be transmitted are coded in a coding device (202) and are combined into coded data blocks (125), the coded data blocks (125) are transformed into a multitone signal (303) in an inverse transformation device (203), the at least one multitone symbol (208) is converted into an analog transmitter signal (211) in a digital-to-analog converter (204), and the analog transmitter signal (211) is transmitted via a transmission channel (102).

Abstract: The invention relates to a method for reducing the crest factor, comprising the following method steps: (a) IFFT transformation of a data symbol to be transmitted; (b) looking for all peak values within a frame of the IFFT-transformed data symbol the amount of which is above a predetermined threshold; (c) providing a sample correction function; (d) allocating a scaling and phase rotation to the sample correction function according to the amplitude and position of the peak values found; (e) generating a correction signal in the frequency domain from a linear combination of rotated and scaled vectors according to the scaling and position determined; (f) modifying, particularly reducing the peak value of the data symbol to be transmitted by subtracting the correction signal, and IFFT transformation of the peak-value-modified data symbol into the time domain. The invention also relates to a circuit for reducing the crest factor.

Abstract: An analog-to-digital converter system converts an analog input signal into a digital output signal. The analog input signal is converted into a first digital signal by a fed back analog-to-digital conversion. A second digital signal is additionally formed, depending on the analog input signal or on the digital output signal, which, combined with the first digital signal, results in the digital output signal.

Abstract: The invention relates to a method for reducing the crest factor of a data symbol to be transmitted in a multi-carrier data transmission system, in which the data symbol to be transmitted is a function of a multiplicity of signals provided within a predetermined data frame and each of these signals is allocated to a carrier, each carrier occupying in each case at least one frequency from a transmit data spectrum, at least one carrier being reserved which is not provided for the data transmission and the predetermined data frame exhibiting the data symbol and a prefix which is derived from a part of the data symbol, in which peak values within the prefix are also taken into consideration for reducing the crest factor.