Abstract: A wake-up circuit and method are provided for detecting and preventing false positive wake-up events in an electronic device in a sleep mode. Methodology entails producing first, second, and third sensor signals at successive first, second, and third instants in time in response to a physical stimulus detected by a sensor of the wake-up circuit. The first sensor signal is selected to be a reference value. A first difference value is determined between the second sensor signal land the reference value, a second difference value is determined between the third sensor signal and the reference value, and communication of a wake-up signal to the electronic device is prevented when at least one of the first and second difference values fails to exceed a threshold value.

Abstract: A wake-up circuit and method are provided for detecting and preventing false positive wake-up events in an electronic device in a sleep mode. Methodology entails producing first, second, and third sensor signals at successive first, second, and third instants in time in response to a physical stimulus detected by a sensor of the wake-up circuit. The first sensor signal is selected to be a reference value. A first difference value is determined between the second sensor signal and the reference value, a second difference value is determined between the third sensor signal and the reference value, and communication of a wake-up signal to the electronic device is prevented when at least one of the first and second difference values fails to exceed a threshold value.

Abstract: A pipelined decoder for storaging of soft bits and hard bits associated with code blocks of a transmission. The proposed circuit reduces the amount of memory needed at the receiver level for soft bits and hard bits, in a pipelined decoder. Namely, with the solution of the subject application, both the LLRs and hard bits associated with a given code block are available when the CRC value is determined. Hence, the effect obtained non-pipelined decoder is achieved by the pipelined decoder of the subject application. A receiver for a wireless communication system, a method and a computer program are also disclosed.

Abstract: A pipelined decoder for storaging of soft bits and hard bits associated with code blocks of a transmission. The proposed circuit reduces the amount of memory needed at the receiver level for soft bits and hard bits, in a pipelined decoder. Namely, with the solution of the subject application, both the LLRs and hard bits associated with a given code block are available when the CRC value is determined. Hence, the effect obtained non-pipelined decoder is achieved by the pipelined decoder of the subject application. A receiver for a wireless communication system, a method and a computer program are also disclosed.

Abstract: A supported palladium-gold catalyst is produced under mild conditions using a commonly available base, such as sodium hydroxide (NaOH) or sodium carbonate (Na2CO3). In this method, support materials and a base solution are mixed together and the temperature of the mixture is increased to a temperature above room temperature. Then, palladium salt and gold salt are added to the mixture while maintaining the pH of the mixture to be greater than 7.0 and keeping the mixture at a temperature above room temperature. This is followed by cooling the mixture while adding acetic acid to maintain the pH of the mixture to be within a desired pH range, filtering out the supported palladium-gold particles, washing with a pH buffer solution and calcining.

Abstract: A supported palladium-gold catalyst is produced under mild conditions using a commonly available base, such as sodium hydroxide (NaOH) or sodium carbonate (Na2CO3). In this method, support materials and a base solution are mixed together and the temperature of the mixture is increased to a temperature above room temperature. Then, palladium salt and gold salt are added to the mixture while maintaining the pH of the mixture to be greater than 7.0 and keeping the mixture at a temperature above room temperature. This is followed by cooling the mixture while adding acetic acid to maintain the pH of the mixture to be within a desired pH range, filtering out the supported palladium-gold particles, washing with a pH buffer solution and calcining.

Abstract: A supported palladium-gold catalyst is produced under mild conditions using a commonly available base, such as sodium hydroxide (NaOH) or sodium carbonate (Na2CO3). In this method, support materials and a base solution are mixed together and the temperature of the mixture is increased to a temperature above room temperature. Then, palladium salt and gold salt are added to the mixture while maintaining the pH of the mixture to be greater than 7.0 and keeping the mixture at a temperature above room temperature. This is followed by cooling the mixture while adding acetic acid to maintain the pH of the mixture to be within a desired pH range, filtering out the supported palladium-gold particles, washing with a pH buffer solution and calcining.