Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

Abstract: A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.

Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

Abstract: A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.

Abstract: One aspect of the present invention relates to a semiconductor circuit arrangement and to a method for producing the latter. One aspect of the invention is that, as a result of a connecting trench structure and an isolation trench structure of a semiconductor circuit being in direct spatial proximity with respect to one another, an additional capacitor device is formed. The capacitance of said capacitor device is connected as a usable capacitance for the semiconductor circuit and is connected to the latter.

Abstract: The present invention relates to a method for producing a vertical transistor, and to a vertical transistor. A sacrificial gate oxide and a sacrificial gate electrode are used during the production of the vertical transistor to makes it possible to considerably reduce or entirely avoid negative effects that normally result from the production of insulation structures between the vertical transistors. In particular, broadening of the gate oxide at the edge of the gate electrode can be prevented, and the edge of the gate electrode can be influenced deliberately. This allows vertical transistors to be produced having a current/voltage characteristic that can be adjusted specifically. In particular, vertical transistors can be produced having a pronounced corner effect.

Abstract: A memory device has a plurality of memory cells, wherein each memory cell has a trench capacitor formed in a semiconductor substrate and an access transistor for it. Each access transistor has a first contact region connected to an internal electrode of the trench capacitor, a second contact region to a bit line and a control electrode region, wherein the control electrode regions of neighboring access transistors are connected by a word line formed in the semiconductor substrate.

Abstract: The present invention relates to a method for producing a vertical transistor, and to a vertical transistor. A sacrificial gate oxide and a sacrificial gate electrode are used during the production of the vertical transistor to makes it possible to considerably reduce or entirely avoid negative effects that normally result from the production of insulation structures between the vertical transistors. In particular, broadening of the gate oxide at the edge of the gate electrode can be prevented, and the edge of the gate electrode can be influenced deliberately. This allows vertical transistors to be produced having a current/voltage characteristic that can be adjusted specifically. In particular, vertical transistors can be produced having a pronounced corner effect.

Abstract: A memory device has a plurality of memory cells, wherein each memory cell has a trench capacitor formed in a semiconductor substrate and an access transistor for it. Each access transistor has a first contact region connected to an internal electrode of the trench capacitor, a second contact region to a bit line and a control electrode region, wherein the control electrode regions of neighboring access transistors are connected by a word line formed in the semiconductor substrate.

Abstract: A semiconductor memory is fabricated with a vertical transistor situated in an upper section of a trench above a trench capacitor. First, an auxiliary insulation layer is applied to the conductive material of an inner electrode or to a connecting material of the trench capacitor. The connecting material is situated on the inner electrode, so that, during an epitaxial deposition, semiconductor material grows only on the uncovered sidewalls in the upper section of the trench. A nitride layer, is deposited conformally and the residual cavity between the inner electrode and the epitaxial semiconductor layer is filled with a doped further conductive material. The nitride layer isolates the epitaxial semiconductor layer from the further conductive material, so that no crystal lattice defects can propagate from there into the epitaxial semiconductor layer. Dopants are outdiffused from the further conductive material into the epitaxial semiconductor layer to form a doping region.

Abstract: A method is provided for manufacturing a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell. In this method, the two spacers of the gate electrode lying opposite one another and the gate path applied on the trench insulation of the memory cell serve as part of the mask that is employed for etching the contact trench and in which the buried bridge of the trench capacitor is subsequently generated. As a result, the position of that sidewall of the bridge facing toward the gate electrode is generated in self-aligning fashion relative to the gate electrode. This avoids photolithographic tolerances in the positioning of the bridge relative to the gate electrode.

Abstract: A memory device has a plurality of memory cells, wherein each memory cell has a trench capacitor formed in a semiconductor substrate and an access transistor for it. Each access transistor has a first contact region connected to an internal electrode of the trench capacitor, a second contact region to a bit line and a control electrode region, wherein the control electrode regions of neighboring access transistors are connected by a word line formed in the semiconductor substrate.

Abstract: A method is provided for manufacturing a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell. In this method, the two spacers of the gate electrode lying opposite one another and the gate path applied on the trench insulation of the memory cell serve as part of the mask that is employed for etching the contact trench and in which the buried bridge of the trench capacitor is subsequently generated. As a result, the position of that sidewall of the bridge facing toward the gate electrode is generated in self-aligning fashion relative to the gate electrode. This avoids photolithographic tolerances in the positioning of the bridge relative to the gate electrode.

Abstract: For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal transformation process and thereby carry out the thermally activated diffusion of a dopant in a substantially directed form, in particular in substantially a preferential direction, by interaction of a provided dopant with a transforming interfacial region.

Abstract: A semiconductor memory is fabricated with a vertical transistor situated in an upper section of a trench above a trench capacitor. First, an auxiliary insulation layer is applied to the conductive material of an inner electrode or to a connecting material of the trench capacitor. The connecting material is situated on the inner electrode, so that, during an epitaxial deposition, semiconductor material grows only on the uncovered sidewalls in the upper section of the trench. A nitride layer, is deposited conformally and the residual cavity between the inner electrode and the epitaxial semiconductor layer is filled with a doped further conductive material. The nitride layer isolates the epitaxial semiconductor layer from the further conductive material, so that no crystal lattice defects can propagate from there into the epitaxial semiconductor layer. Dopants are outdiffused from the further conductive material into the epitaxial semiconductor layer to form a doping region.

Abstract: The field-effect transistor has an insulated gate, a source electrode, a drain electrode, and an inversion channel between the source and drain electrodes and underneath the gate electrode. The gate electrode is fabricated from a material which does not have a permitted energy state in the energy interval which is used to control the charge carrier density in the inversion channel between the source electrode and the drain electrode.

Abstract: The present invention relates to a method for producing a vertical transistor, and to a vertical transistor. A sacrificial gate oxide and a sacrificial gate electrode are used during the production of the vertical transistor to makes it possible to considerably reduce or entirely avoid negative effects that normally result from the production of insulation structures between the vertical transistors. In particular, broadening of the gate oxide at the edge of the gate electrode can be prevented, and the edge of the gate electrode can be influenced deliberately. This allows vertical transistors to be produced having a current/voltage characteristic that can be adjusted specifically. In particular, vertical transistors can be produced having a pronounced corner effect.

Abstract: For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal transformation process and thereby carry out the thermally activated diffusion of a dopant in a substantially directed form, in particular in substantially a preferential direction, by interaction of a provided dopant with a transforming interfacial region.

Abstract: The field-effect transistor has an insulated gate, a source electrode, a drain electrode, and an inversion channel between the source and drain electrodes and underneath the gate electrode. The gate electrode is fabricated from a material which does not have a permitted energy state in the energy interval which is used to control the charge carrier density in the inversion channel between the source electrode and the drain electrode.