Abstract: Low-resistance diffused regions useful as current-supply paths in IC MOS semiconductor circuits in silicon-gate technology are produced by forming a metal silicide on a doped polysilicon layer positioned on a substrate, applying a SiO.sub.2 layer over the silicide layer, structuring the resultant SiO.sub.2 -silicide-polysilicon triple layer in such a manner that areas of the substrate where the low resistance diffused regions are desired remain covered, thereafter executing gate oxidation and completing fabrication of the desired circuit.

Abstract: In an exemplary embodiment, after underetching a first polysilicon layer beneath spaced SiO.sub.2 cover layers to produce pairs of confronting SiO.sub.2 overhangs with gaps therebetween, and providing an insulating layer at the end faces of the spaced poly-Si-1 electrodes formed from the first polysilicon layer, a second polysilicon layer is produced by chemical vapor deposition (CVD) so as to fill the cavities beneath the SiO.sub.2 overhangs via the gaps between each pair of confronting overhangs. The second polysilicon layer is then etched away so as to leave intervening self-adjusting, nonoverlapping poly-Si-2 electrodes formed from the second polysilicon layer with surfaces terminating for example slightly below the upper surfaces of the SiO.sub.2 cover layers. For a center-to-center spacing of poly-Si-1 electrodes of six microns, the SiO.sub.2 overhangs may have an extent (e.g. 0.7 microns) about equal to the electrode layer thickness (e.g. 0.8 microns).

Abstract: In an exemplary embodiment, a first polysilicon layer is provided with a SiO.sub.2 mask, and the first polysilicon layer is etched away under the SiO.sub.2 mask to produce SiO.sub.2 overhangs of a lateral extent corresponding to about twice the edge position error (.sup..+-. s). Then when second polysilicon layers are produced by means of chemical vapor deposition (CVD), to occupy the cavities under the SiO.sub.2 overhangs, the desired nonoverlapping poly-Si-2 electrodes result after definition of those poly-Si-2 electrodes by known lithographical techniques.

Abstract: A method of producing integrated MOS circuits via silicon gate technology with self-adjusting contacts by using silicon nitride masking. In accordance with this method, after etching contact holes for the formation of contacts between monocrystalline doped regions (5) and polysilicon regions (4, 8), or metal interconnections (12), an insulating layer 10 is produced. This insulating layer is produced, after appropriate masking with an oxidation-inhibiting silicon nitride layer of the regions to be connected, from a layer (8) which is additionally applied and doped to correspond to the doped regions in the silicon substrate, and which is converted by local oxidation into the insulating layer (10). This process provides extremely high packing density of circuit elements.

Abstract: An MIS-field effect transistor comprising a semiconductor member provided with an overlying insulating layer and having a source zone and a drain zone of a first conductivity type provided with respective contacting electrodes, and a gate-electrode layer disposed therebetween, with each of said areas being surrounded by a less heavily doped area of the same conductivity type. At the source side, an additional area abuts the source zone and extends to the semiconductor surface beneath the gate-electrode layer, forming a channel having a very short length. The various dopings having different penetration depths are produced by differential implantation. A windowed mask, having windows with beveled edges at the drain-zone and the source zone, is utilized as an implantation mask, which advantageously is formed by the insulating layer and/or by the gate-electrode layer.

Abstract: A radiation mask having a masking structure and a carrier therefore, for the production of structural configurations in photosensitive resists by x-ray radiation, with the carrier having registration marks thereon, in which the carrier comprises a layer of approximately 3 to 10 .mu.m in thickness, which layer is formed of material penetratable both by x-rays and by radiation in the visible part of the spectrum, the carrier material preferably being polyimide resin or silicon dioxide produced thermally or by a sputtering technique. In a further embodiment the carrier may comprise a first layer of silicon dioxide and a second supporting layer of polyimide resin.

Abstract: A thermal element arrangement having a plurality of thermal elements connected in series, and in which an insulation layer has thereon a plurality of metal conductor paths situated on the semiconductor substrate. Each thermal element has one of the metal conductor paths forming a first leg and a semiconductor region forming a second leg. A thermal contact is included having a metal semiconductor contact with the respective semiconductor regions. The semiconductor substrate is less than 10 .mu.m thick in the region where the thermal contacts which are to be heated up is located. Elsewhere, the substrate has a thickness of more than 200 .mu.m which is in that region in which there are situated the contacts which are to be kept cold during the operation of the arrangement. One preferred arrangement has the thermal contacts to be heated during operation surrounded in a star-shaped manner by thermal contacts which are to be kept cold.

Abstract: A process for producing fine structures having an order of magnitude of 1 .mu.m without a loss of dimension relative to a mask on a base such as a semiconductor device having electrode structures characterized by providing a base having a surface which is either etchable or is provided with an auxiliary etchable layer, providing a mask on the surface, which mask has openings corresponding to the fine structure of material to be applied on the surface, providing an etching agent which attacks the surfaces of the base without attacking the mask, etching the uncovered portions of the base until an under-etching of predetermined width exists beneath the edges of the mask, depositing the layer of material on the entire surface, controlling the amount of depositing so the layer of material being deposited on the mask and on the etched surfaces of the base are not in contact with each other, and subsequently removing the mask with the layer of material deposited thereon.

Abstract: In a method for the automatic adjustment of semiconductor wafers, adjustment marks are arranged on the surface of the wafer to be adjusted. Light is emitted through a transparent body with an attached mask. The transparent body and mask are displaced so that adjustment patterns on the mask are aligned with respect to the wafer adjustment patterns. A shutter below the mask ensures that only light beams which pass through the adjustment patterns of the mask hit the surface of the semiconductor wafer. Light beams passing through the adjustment patterns of the mask are directed onto the surface of the semiconductor wafer by an objective. The wafer reflects the light back through the objective, shutter apertures and adjustment patterns. The reflected back beams of light are detected by light sensitive elements and the orientation of the mask and transparent body is arranged such that minimum reflected light is received at the light sensitive elements.

Abstract: A method of making a bipolar integrated circuit which requires neither an epitaxial layer nor a buried layer. The required doping of a semiconductor substrate, e.g., silicon, is obtained by a series of etching steps alternated with ion implantation steps of a selected impurity type, and heat treatment steps. The emitter and collector zones of a transistor are formed on sloping walls of adjacent troughs formed in a semiconductor substrate. The base zone of a transistor is formed on the confronting sloping wall of one of these troughs. Lead conductors are located in the troughs along sloping wall portions of the troughs.

Abstract: Described are novel semiconductor structures having a protective passivating layer made from photo- or radiation cross-linking of selected reactive sites of a soluble pre-polymer which is a poly-addition or poly-condensation product of a polyfunctional carbocyclic and/or heterocyclic compound having reactive groups for condensation or addition as well as photoreactive or radiation-reactive groups capable of further polymerization or dimerization. Selected non-cross-linked portions of the passivating layer may be removed by dissolution to form contact points for various useful semiconductor and capacitor components.