Patents by Inventor Dieuwert Peter Nicolaas Mul

Dieuwert Peter Nicolaas Mul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146346
    Abstract: A method of applying an activation scheme to a digitally controlled segmented RF power transmitter having a plurality of adjacent segments (3), each segment (3) having an associated activation area, the segments (3) being controlled by one or more code words (CWD) The method includes controlling segments (3) by activating a specific segment (3) using an activation scheme for activating specific ones of the segments (3) depending on the code word (CWD), the activation scheme starting from center ones of the plurality of segments (3) towards outer ones of the plurality of segments (3) for increasing code word (CWD) values. This method can be applied in any digitally controlled segmented RF power transmitter, be it in polar or Cartesian implementations, and in single ended or push-pull output configurations.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 2, 2024
    Applicant: TECHNISCHE UNIVERSITEIT DELFT
    Inventors: Dieuwert Peter Nicolaas Mul, Robert Jan Bootsman, Mohammad Reza Beikmirza, Seyed Morteza Alavi, Leonardus Cornelis Nicolaas de Vreede
  • Publication number: 20240146503
    Abstract: Digitally controlled segmented RF power transmitter with a digital processing part (2) and an RF power amplification part (3) having a plurality of segments (122). The digital processing part (2) has a clock generation block (5) being arranged to generate n equi-phased clock signals with a 50% duty-cycle (fLO,x_50%; Cx), and a sign-bit phase mapper unit (11) being arranged to receive the n equi-phased clock signals (fLO,x_50%; Cx), and sign signals (SignI, SignQ; sign bits), and to output a set of m, m?n, phase mapped clock signals with a 50% duty-cycle (CLKy,50%; Cy) using a predetermined phase swapping scheme. Each of the plurality of segments (122) comprises logic circuitry (12) receiving the set of m phase-mapped clock signals with a 50% duty-cycle (CLKy,50%; Cy), and being arranged to provide the respective segment driving signal with a duty-cycle z of less than 50%.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 2, 2024
    Applicant: Technische Universiteit Delft
    Inventors: Mohammad Reza Beikmirza, Leonardus Cornelis Nicolaas de Vreede, Robert Jan Bootsman, Dieuwert Peter Nicolaas Mul, Seyed Morteza Alavi, Yiyu Shen
  • Publication number: 20230139209
    Abstract: An RF transmitter (1) having a gate-segmented power output stage (2) and a digital driver (5). The gate-segmented power output stage (2) includes a field-effect transistor with a plurality of gate fingers (32) and drain fingers (31) that define a gate periphery. The field-effect transistor comprises a plurality of power output stage segments (3) that each correspond to a respective part of the gate periphery, and that each have a respective power output stage segment input (4). The digital driver (5) has control outputs (6) which are connected to corresponding ones of the respective power output stage segment inputs (4), and is configured for individually switching each of the power output stage segments (3) between an on mode and a cut-off mode in dependence of one or more input signals to obtain a modulated RF carrier signal at an output (7) of the gate-segmented power output stage (2).
    Type: Application
    Filed: February 5, 2021
    Publication date: May 4, 2023
    Applicant: Technische Universiteit Delft
    Inventors: Leonardus Cornelis Nicolaas de Vreede, Seyed Morteza Alavi, Robert Jan Bootsman, Mohammad Reza Beikmirza, Dieuwert Peter Nicolaas Mul, Rob Heeres, Freerk van Rijs