Patents by Inventor Diganta Baishya

Diganta Baishya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks
    Patent number: 8842766
    Abstract: An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: September 23, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Indu Prathapan, Anjana Ghosh, Diganta Baishya, Sundarrajan Rangachari, Sankar Prasad Debnath, Ranjit Kumar Dash, Srinath Mathur Ramaswamy
  • APPARATUS AND METHOD FOR REDUCING INTERFERENCE SIGNALS IN AN INTEGRATED CIRCUIT USING MULTIPHASE CLOCKS
    Publication number: 20110241747
    Abstract: An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Inventors: INDU PRATHAPAN, Anjana Ghosh, Diganta Baishya, Sundarrajan Rangachari, Sankar Prasad Debnath, Ranjit Kumar Dash, Srinath Mathur Ramaswamy