Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the bridge die. The bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

Abstract: An apparatus is provided which comprises: a plurality of interconnects to couple a silicon interposer to a substrate; and a landing pad configured in a non-circle shape, wherein the plurality of interconnects are adjacent to the landing pad at one end of the plurality of interconnects through a plurality of vias.

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.

Abstract: Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.

Abstract: Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

Abstract: An apparatus is provided which comprises: a plurality of interconnects to couple a silicon interposer to a substrate; and a landing pad configured in a non-circle shape, wherein the plurality of interconnects are adjacent to the landing pad at one end of the plurality of interconnects through a plurality of vias.

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Abstract: Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Abstract: An apparatus is provided comprising: first die, wherein a first plurality of interconnect structures is formed on the first die; one or more layers, wherein a first surface of the one or more layers is attached to the first plurality of interconnect structures; a second plurality of interconnect structures formed on a second surface of the one or more layers; and a second die, wherein a third plurality of interconnect structures is formed on the second die, wherein a first interconnect structure of the first plurality of interconnect structures is electrically connected to a second interconnect structure of the second plurality of interconnect structures through the one or more layers, and wherein the first die is mounted on the second die such that the second interconnect structure of the second plurality of interconnect structures is attached to a third interconnect structure of the third plurality of interconnect structures.

Abstract: A user-customizable locking assembly includes a user-customizable key, a user-customizable key receiver, and a key receiver receptacle. Each of the user-customizable key, a user-customizable key receiver, and a key receiver receptacle includes a physical unclonable function (PUF) circuit configured to provide a PUF response in response to receiving a challenge signal. The PUF circuits of the user-customizable key and a user-customizable key receiver include personalization fuses that allow a user to further personalize or change the PUF response produced by the corresponding PUF circuits. The key receiver receptacle also includes anti-theft fuses, which are activated if the user-customizable key receiver is removed from the key receiver receptacle. In use, a protected system may utilize the PUF responses from the each of the PUF circuits to authenticate the user-customizable locking assembly.

Abstract: An apparatus is provided comprising: a substrate; a die having a first side and a second side, wherein the die is mounted on the substrate such that the first side of the die faces the substrate, and wherein at least a portion of the first side of the die is removed to form a recess in the die; and a component, wherein at least a part of the component is disposed within the recess in the first die.

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a top surface and a vertical surface extending downward from the top surface. The top surface and the vertical surface can define an edge. The electronic device package can also include an electronic component disposed on the top surface of the substrate and electrically coupled to the substrate. In addition, the electronic device package can include an underfill material disposed at least partially between the electronic component and the top surface of the substrate. A lateral portion of the underfill material can extend from the electronic component to at least the edge. Associated systems and methods are also disclosed.

Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.

Abstract: An integrated circuit (IC) package including a substrate comprising a dielectric, and at least one bridge die embedded in the first dielectric. The embedded bridge die comprises a plurality of through-vias extending from a first side to a second side and a first plurality of pads on the first side and a second plurality of pads on the second side. The first plurality of pads are interconnected to the second plurality of pads by the plurality of through-vias extending vertically through the bridge die. The second plurality of pads is coupled to a buried conductive layer in the substrate by solder joints or by an adhesive conductive film between the second plurality of pads of the bridge die and conductive structures in the buried conductive layer, and wherein the adhesive conductive film is over a second dielectric layer on the bridge die.

Abstract: An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a top surface and a vertical surface extending downward from the top surface. The top surface and the vertical surface can define an edge. The electronic device package can also include an electronic component disposed on the top surface of the substrate and electrically coupled to the substrate. In addition, the electronic device package can include an underfill material disposed at least partially between the electronic component and the top surface of the substrate. A lateral portion of the underfill material can extend from the electronic component to at least the edge. Associated systems and methods are also disclosed.