Patents by Inventor Dilder Chowdhury

Dilder Chowdhury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Half-bridge semiconductor device
    Patent number: 11942401
    Abstract: This disclosure relates to a discrete half bridge semiconductor device including a first cascode arrangement and a second cascode arrangement. Each of the first cascode and second cascode arrangements include a high voltage FET device die and a low voltage FET device die; and the source of the high voltage FET device die is mounted on and connected to a drain of the low voltage FET device die. The source of the low voltage FET device die and gate of the high voltage FET device die are connected to a drain terminal of the high voltage FET device die of the second cascode arrangement at a common connection pad.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: March 26, 2024
    Assignee: Nexperia B.V.
    Inventors: Dilder Chowdhury, Ricardo Lagmay Yandoc, Saurabh Pandey
  • SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20220262712
    Abstract: A semiconductor device is provided, including a MOSFET die, a first GaN die and a second GaN die. The first GaN die and the second GaN die are arranged in a cascode arrangement. The second GaN die is positioned in an inverted orientation. The MOSFET die controls the first GaN die and the second GaN die.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 18, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Dilder Chowdhury, Ilyas Dchar
  • Half-Bridge Semiconductor Device
    Publication number: 20210111107
    Abstract: This disclosure relates to a discrete half bridge semiconductor device including a first cascode arrangement and a second cascode arrangement. Each of the first cascode and second cascode arrangements include a high voltage FET device die and a low voltage FET device die; and the source of the high voltage FET device die is mounted on and connected to a drain of the low voltage FET device die. The source of the low voltage FET device die and gate of the high voltage FET device die are connected to a drain terminal of the high voltage FET device die of the second cascode arrangement at a common connection pad.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 15, 2021
    Applicant: NEXPERIA B.V.
    Inventors: Dilder Chowdhury, Ricardo Lagmay Yandoc, Saurabh Pandey