Abstract: A hash accelerator of a cache memory may receive a query from a processor comprising the cache memory, the query to comprise an input key and an operation to be performed based on a hash table stored in the cache memory. The hash accelerator may determine whether an entry associated with the input key exists in a lock board of the hash accelerator. The hash accelerator may process the query based on whether the entry exists in the lock board.

Abstract: A DNN accelerator includes a multiplication controller controlling whether to perform matrix computation based on weight values. The multiplication controller reads a weight matrix from a WRAM in the DNN accelerator and determines a row value for a row in the weight matrix. In an embodiment where the row value is one, a first switch sends a read request to the WRAM to read weights in the row and a second switch forms a data transmission path from an IRAM in the DNN accelerator to a PE in the DNN accelerator. The PE receives the weights and input data stored in the IRAM and performs MAC operations. In an embodiment where the row value is zero, the first and second switches are not triggered. No read request is sent to the WRAM and the data transmission path is not formed. The PE will not perform any MAC operations.