Abstract: A method, system, and computer program product to characterize and adaptively instantiate timing abstracts to perform timing analysis of an integrated circuit include generating an adaptable timing abstract for one or more macro models of a macro, the macro including two or more primitives of a component of the integrated circuit, the adaptable timing abstract being a parameterized timing model with at least one aspect represented by two or more models, and estimating requirements for the timing analysis, the requirements including accuracy, runtime, or memory requirements. Selecting a specific timing abstract, obtained by setting parameters of the adaptable timing abstract, is to perform the timing analysis based on the requirements.

Abstract: A method, system, and computer program product to characterize and adaptively instantiate timing abstracts to perform timing analysis of an integrated circuit include generating an adaptable timing abstract for one or more macro models of a macro, the macro including two or more primitives of a component of the integrated circuit, the adaptable timing abstract being a parameterized timing model with at least one aspect represented by two or more models, and estimating requirements for the timing analysis, the requirements including accuracy, runtime, or memory requirements. Selecting a specific timing abstract, obtained by setting parameters of the adaptable timing abstract, is to perform the timing analysis based on the requirements.

Abstract: Embodiments of the present invention relate to determining process variations using device threshold sensitivities. A computing device determines first and second threshold voltages for first and second transistors, respectively, wherein the first and second transistors are included in an integrated circuit and are n-channel and p-channel field effect transistors, respectively. The computing device also determines process parameters that are associated with the integrated circuit using a combination of determined first and second threshold voltages, wherein the process parameter reflects random sensitivities, timing delay differences, timing delay and slew rate changes, and/or variations between low, high, and regular threshold voltages which are associated with the first and second transistors.

Abstract: A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.

Abstract: A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.