Abstract: According to one aspect of the present disclosure, a decoder is provided. The decoder may include a first processing circuit to: obtain a check formula and check formula weight based on a codeword to be decoded in a current iteration and a check matrix; a second processing circuit to: obtain energy of the codeword to be decoded based on the check formula, the check matrix and a flipping state of the codeword to be decoded; a processor to: in a first iteration, select a preset threshold sequence as an initial threshold sequence based on the check formula weight; and assign a flipping threshold in the initial threshold sequence to a bit flipping circuit; and the bit flipping circuit to: output a codeword to be decoded in a following iteration based on a result of a comparison between energy of the codeword to be decoded and the flipping threshold.

Abstract: In certain aspects, a memory controller includes a logical-to-physical (L2P) search engine. The L2P search engine is configured to maintain an L2P mapping table that maps logical addresses to physical addresses, respectively. The L2P search engine is also configured to organize the physical addresses mapped by the L2P mapping table into address categories based on at least one address boundary.

Abstract: In certain aspects, a memory controller includes a logical-to-physical (L2P) search engine. The L2P search engine is configured to maintain an L2P mapping table that maps logical addresses to physical addresses, respectively. The L2P search engine is also configured to organize the physical addresses mapped by the L2P mapping table into address categories based on at least one address boundary.

Abstract: Examples of the present disclosure disclose a shift circuit, a data selector, a memory controller, and a memory system. The shift circuit includes: a data selector, including a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal, wherein the first input terminal is configured to access a first control signal, the third input terminal is configured to access a second control signal, the first control signal and the second control signal are inverse signals to each other, the fourth input terminal is configured to access a corresponding first bit in input data, and the second input terminal is configured to access a corresponding second bit in the input data; and when the first control signal is in a first state, the output terminal outputs an inverted value of the second bit.

Abstract: Examples provide for error correction. The error correction includes: obtaining first soft data according to first hard read data and cached second hard read data after hard decision decoding for the first hard read data fails, wherein the first hard read data is read according to a first hard read voltage, and the second hard read data is read according to a second hard read voltage before reading the first hard read data; and performing first soft decision decoding according to the first soft data and the first hard read data, or according to the first soft data and the second hard read data, wherein the first hard read voltage is one of a plurality of re-read voltages corresponding to a read command; and the second hard read voltage is an initial read voltage or a re-read voltage of the plurality of re-read voltages except the first hard read voltage.

Abstract: According to one aspect of the present disclosure, a decoder is provided. The decoder may include a cache module. The cache module may be configured to cache soft data related to a codeword to be decoded. The decoder may include a flip-indication module. The flip-indication module may be configured to obtain the soft data from the cache module. The flip-indication module may be configured to, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration and with assistance of the soft data, a number of parity checks not satisfied by bits in the codeword to be decoded.

Abstract: Examples provide for error correction. The error correction includes: obtaining first soft data according to first hard read data and cached second hard read data after hard decision decoding for the first hard read data fails, wherein the first hard read data is read according to a first hard read voltage, and the second hard read data is read according to a second hard read voltage before reading the first hard read data; and performing first soft decision decoding according to the first soft data and the first hard read data, or according to the first soft data and the second hard read data, wherein the first hard read voltage is one of a plurality of re-read voltages corresponding to a read command; and the second hard read voltage is an initial read voltage or a re-read voltage of the plurality of re-read voltages except the first hard read voltage.

Abstract: In certain aspects, a memory controller includes a logical-to-physical (L2P) search engine. The L2P search engine is configured to maintain an L2P mapping table that maps logical addresses to physical addresses, respectively. The L2P search engine is also configured to organize the physical addresses mapped by the L2P mapping table into address categories based on at least one address boundary.