Abstract: Heterogeneous multiplier circuitry is provided with an interface to a configuration register to access configuration information, where the configuration information identifies respective data formats of a first operand and a second operand to be used in a first multiplication operation, where the first operand is in a first data format including a first numerical representation and the second operand is in a different, second data format including a different, second numerical representation. The heterogeneous multiplier circuitry includes an operand modifier to modify the second operand to generate a modified second operand, and further includes a multiplier to perform multiplication of the first operand and the modified second operand to generate a result in the first data format.

Abstract: In one embodiment, a system employing selective noise tolerance modes of memory operation in accordance with one aspect of the present description can reduce levels of memory operation power consumption as compared to those achieved by many prior devices. In one embodiment, each noise tolerance mode has an associated level of input power to a memory. For example, in one embodiment, the greater the degree of tolerance for noise in the data of a workload being processed, the greater the reduction in memory input power and the greater the resultant reduction in power consumption. Other aspects and advantages are described.