Abstract: A casting method includes: forming a seed, the seed having a first end and a second end, the forming including bending a seed precursor; placing the seed second end in contact or spaced facing relation with a chill plate; contacting the first end with molten material; and cooling and solidifying the molten material so that a crystalline structure of the seed propagates into the solidifying material. The forming further included reducing a thickness of the seed proximate the first end relative to a thickness of the seed proximate the second end.

Abstract: A communication subsystem used in an aircraft entertainment system employs a microcontroller and a dual-ported RAM to relieve burden from the host processor in handling low-level operations in communicating with external devices. The host processor and the microcontroller accesses the dual-ported RAM by testing the semaphore to determine if the DPRAM is available. If available, the processor and/or the microcontroller will read/write the messages from/to the DPRAM as appropriate. The microcontroller controls the communication interface controllers directly and will send messages read from the DPRAM to the CICs or write to the DPRAM messages received from the CICs without host processor's intervention. The microcontroller also performs other low-level operations such as header/trailer processing and error checking/correcting free from the host processor.

Abstract: The interrupt regenerator circuit converts the transition signal caused by a passenger's data entry in an aircraft entertainment system into a triggering signal. The triggering signal triggers a delay element consisting of cascadable one-shot devices. The timing intervals for the outputs of these one-shot devices are programmable through the selection of proper values for the resistors and capacitors. The interrupt signal is de-asserted by the host processor when the host processor responds to the interrupt. The delayed interrupt signal is then gated by the interrupt signal itself to regenerate the interrupt signal to the host processor.

Abstract: A plurality of identical circuit board identification generators are individually located on an associated plurality of circuit boards in a computer system, each generator providing a unique identification for each associated circuit board. Identification numbers are automatically and sequentially generated by the generators upon the initial system turn on or upon a resetting of the system. The generators comprise a counter and logic circuitry for enabling the counters. The counters are initially disabled and pre-set to a maximum count. The first counter is then enabled and counts from the maximum to zero, and delivers an enable signal to the logic circuitry in the next circuit board to enable that counter. The enable signals propagate from board to board until the last board commences its count, at which time all counters are disabled. In this manner, N circuit boards will be identified as boards "O" through "N-1.