Abstract: In one embodiment, an apparatus and method for concurrent testing of multiple embedded arrays is disclosed. In one embodiment, the apparatus comprises a built-in self test (BIST) engine coupled to a plurality of arrays having different sizes to generate test packets targeted to an array with the most entries among the plurality of arrays, a plurality of address space control logic each associated with an array of the plurality of arrays, the address space control logic to adjust a broadcast address of the test packets to match an address space of its associated array, and an array width independent concurrent response evaluator (AWIC-RE) coupled to the plurality of arrays.

Abstract: A system for scan testing a device under test (“DUT”) in which the clock speed of the DUT differs from test equipment. A plurality of scan-flops in the DUT form a scan-wheel, which defines a closed scan path. The Data bits in the scan path are shifted through a scan-wheel controller based on the DUT clock speed, so that a different bit passes through the scan-wheel controller on each clock cycle of the DUT. Test data is only loaded by replacing the data bit as it passes through the controller. The different clock rates of the DUT and the test equipment define a scan wheel ratio, which is used to determine the number of times that the scan-wheel must rotate before all old data bits are unloaded and replaced by newly loaded bits, and which also determines when data bits passing through the controller will be unloaded and replaced.

Abstract: A self-repair method for a random access memory (RAM) array comprises writing a value to the memory array, reading a value from the memory array and comparing the read and write values to identify faulty memory cells in the memory array. An address of a newly-discovered faulty memory cell is compared to at least one address of at least one previously-discovered faulty memory cell. The address of the newly discovered faulty memory cell is stored if a column or row address of the newly-discovered faulty cell does not match any column or row address, respectively, of a previously-discovered faulty memory cell. Flags are set to indicate that a spare row or a spare column must replace the row or column, respectively, identified by the address of the previously-discovered faulty memory cell, if the row or column address of the newly-discovered memory cell matches the respective row or column address of the previously-discovered faulty memory cell.

Abstract: A method and apparatus for built in self test, BIST, of content addressable memory, CAM, and associated random access memory, RAM, is described. The method and apparatus may most beneficially be used for difficult to test situations such as embedded CAM or other memory types. There are no external memory read operations to determine the contents of a memory location, so little additional circuitry or overhead, such as separate read ports, is required on the embedded memory for implementation of the BIST. Only a number generator, a shift register and an OR gate with inputs from each of the CAM word match lines are added to the circuit in which the memory is embedded. The test uses a set of unique data patterns, each one spaced from the others by two bit locations, a walking inversion test, and a complement and reverse pattern test to determine what type of error and the error location.

Abstract: A boundary scan based VIH/VIL test scheme for a clock forwarded interface of an IEEE 1149.1 Standard-compliant electronic component is provided. The Standard-compliant component has a test access port (TAP) and a forwarded clock interface including data and forwarded clock inputs for receiving signals from and sending signals to external circuitry during a test operation. Connected to each of such component's data inputs is a clocked and an unclocked input buffer. Coupled to the TAP is an instruction register for receiving Standard defined and other test instructions provided by the external circuitry at the TAP. Also coupled to the TAP is a chain of boundary scan cells, each associated with a different one of the input pins and connected to the output of each input buffer coupled thereto, and a TAP controller for generating control signals to capture and shift data through the boundary scan cells in response to test instructions received by the instruction register.

Abstract: A technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus configuration. The technique assigns a code consisting of predetermined number of asserted bits to each portion of the memory. If a failure condition is detected, the code associated with that portion is asserted onto the bus. Because the code for each memory portion always has a given number of asserted bits, a multi-bit failure situation can be distinguished from a single bit failure situation by counting the number of bits asserted.

Abstract: Apparatus and method for hierarchical, centralized boundary-scan fault-testing of extended electronic circuits, including inter-board testing, within a unified, standard protocol. During this testing, each board is "viewable" from the central test control in the same way that it is viewable when standing alone, before being incorporated into an extended system. The preferred embodiment of the invention is based on IEEE Std 1149.1, and is to be used with integrated circuits compliant with that standard. Because of this, the IEEE Std 1149.1 test elements--including but not limited to extensive micro-code--prepared for the testing of the board individually can be incorporated into the system-wide testing. The invention makes use of a "parking" of integrated circuit test rings with any desired test vector in their boundary scan registers, so that they can subsequently be viewed from another board as part of inter-board fault testing.

Abstract: A digital circuit operable in a normal mode and in a test mode including memory elements which each operates as a static latch during the normal mode and operates as a dynamic master-slave flip-flop during the test mode. The digital circuit also includes combinational logic having a plurality of outputs, means operable in the normal mode to connect a combinational logic output to each of the inputs of the memory elements, and means operable in the test mode to connect outputs of memory elements to inputs of other memory elements so as to form a shift register to facilitate testing of complex digital circuits.

Abstract: A built-in test system employs dual-mode feedback shift registers to supply test vectors and evaluate test responses of functional and interface networks of a logic system. Test responses are supplied to a quotient bit compressor which generates a system response signature for comparison with an expected fault-free signature to produce a system pass/fail status signal.